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-rw-r--r--CHANGELOG8
1 files changed, 6 insertions, 2 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 4c38f6e6e..8c88a7db8 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -17,8 +17,12 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "rename -src"
- Added "equiv_opt" pass
- Added "read_aiger" frontend
- - Extended "muxcover -mux{4,8,16}=<cost>"
+ - Added "muxcover -mux{4,8,16}=<cost>"
+ - Added "muxcover -dmux=<cost>"
+ - Added "muxcover -nopartial"
+ - Added "muxpack" pass
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
+ - Fixed sign extension of unsized constants with 'bx and 'bz MSB
Yosys 0.7 .. Yosys 0.8
@@ -32,7 +36,7 @@ Yosys 0.7 .. Yosys 0.8
- Added "write_verilog -decimal"
- Added "scc -set_attr"
- Added "verilog_defines" command
- - Remeber defines from one read_verilog to next
+ - Remember defines from one read_verilog to next
- Added support for hierarchical defparam
- Added FIRRTL back-end
- Improved ABC default scripts