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-rw-r--r--CHANGELOG6
1 files changed, 4 insertions, 2 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 8c88a7db8..4d0c31e28 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -16,12 +16,14 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "gate2lut.v" techmap rule
- Added "rename -src"
- Added "equiv_opt" pass
+ - Added "shregmap -tech xilinx"
- Added "read_aiger" frontend
- Added "muxcover -mux{4,8,16}=<cost>"
- Added "muxcover -dmux=<cost>"
- Added "muxcover -nopartial"
- Added "muxpack" pass
- - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
+ - Added "pmux2shiftx -norange"
+ - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
- Fixed sign extension of unsized constants with 'bx and 'bz MSB
@@ -45,7 +47,7 @@ Yosys 0.7 .. Yosys 0.8
- Added Verilog $rtoi and $itor support
- Added "check -initdrv"
- Added "read_blif -wideports"
- - Added support for systemVerilog "++" and "--" operators
+ - Added support for SystemVerilog "++" and "--" operators
- Added support for SystemVerilog unique, unique0, and priority case
- Added "write_edif" options for edif "flavors"
- Added support for resetall compiler directive