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Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 42 |
1 files changed, 41 insertions, 1 deletions
@@ -2,9 +2,49 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.13 .. Yosys 0.13-dev +Yosys 0.15 .. Yosys 0.15-dev -------------------------- +Yosys 0.14 .. Yosys 0.15 +-------------------------- + + * Various + - clk2fflogic: nice names for autogenerated signals + - simulation include support for all flip-flop types. + - Added AIGER witness file co-simulation. + + * Verilog + - Fixed evaluation of constant functions with variables or arguments with + reversed dimensions + - Fixed elaboration of dynamic range assignments where the vector is + reversed or is not zero-indexed + - Added frontend support for time scale delay values (e.g., `#1ns`) + + * SystemVerilog + - Added support for accessing whole sub-structures in expressions + + * New commands and options + - Added glift command, used to create gate-level information flow tracking + (GLIFT) models by the "constructive mapping" approach + + * Verific support + - Ability to override default parser mode for verific -f command. + +Yosys 0.13 .. Yosys 0.14 +-------------------------- + + * Various + - Added $bmux and $demux cells and related optimization patterns. + + * New commands and options + - Added "bmuxmap" and "dmuxmap" passes + - Added "-fst" option to "sim" pass for writing FST files + - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate", + "-sim-gold" options to "sim" pass for co-simulation + + * Anlogic support + - Added support for BRAMs + Yosys 0.12 .. Yosys 0.13 -------------------------- |