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Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 1 insertions, 3 deletions
@@ -1,7 +1,7 @@ ``` yosys -- Yosys Open SYnthesis Suite -Copyright (C) 2012 - 2019 Clifford Wolf <clifford@clifford.at> +Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above @@ -541,8 +541,6 @@ from SystemVerilog: SystemVerilog files being read into the same design afterwards. - typedefs are supported (including inside packages) - - type identifiers must currently be enclosed in (parentheses) when declaring - signals of that type (this is syntactically incorrect SystemVerilog) - type casts are currently not supported - enums are supported (including inside packages) |