1 files changed, 6 insertions, 48 deletions

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 36a379e34..77d0e94c2 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -312,7 +312,7 @@ struct XAigerWriter
 #if 0
 			toposort.analyze_loops = true;
 #endif
-			bool no_loops = toposort.sort();
+			bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
 #if 0
 			unsigned i = 0;
 			for (auto &it : toposort.loops) {
@@ -326,7 +326,6 @@ struct XAigerWriter
 #endif
 			log_assert(no_loops);
 
-			pool<IdString> seen_boxes;
 			for (auto cell_name : toposort.sorted) {
 				RTLIL::Cell *cell = module->cell(cell_name);
 				log_assert(cell);
@@ -335,47 +334,6 @@ struct XAigerWriter
 				if (!box_module || !box_module->attributes.count("\\abc_box_id"))
 					continue;
 
-				if (seen_boxes.insert(cell->type).second) {
-					auto it = box_module->attributes.find("\\abc_carry");
-					if (it != box_module->attributes.end()) {
-						RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
-						auto carry_in_out = it->second.decode_string();
-						auto pos = carry_in_out.find(',');
-						if (pos == std::string::npos)
-							log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
-						auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos));
-						carry_in = box_module->wire(carry_in_name);
-						if (!carry_in || !carry_in->port_input)
-							log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
-
-						auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1));
-						carry_out = box_module->wire(carry_out_name);
-						if (!carry_out || !carry_out->port_output)
-							log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
-
-						auto &ports = box_module->ports;
-						for (auto jt = ports.begin(); jt != ports.end(); ) {
-							RTLIL::Wire* w = box_module->wire(*jt);
-							log_assert(w);
-							if (w == carry_in || w == carry_out) {
-								jt = ports.erase(jt);
-								continue;
-							}
-							if (w->port_id > carry_in->port_id)
-								--w->port_id;
-							if (w->port_id > carry_out->port_id)
-								--w->port_id;
-							log_assert(w->port_input || w->port_output);
-							log_assert(ports[w->port_id-1] == w->name);
-							++jt;
-						}
-						ports.push_back(carry_in->name);
-						carry_in->port_id = ports.size();
-						ports.push_back(carry_out->name);
-						carry_out->port_id = ports.size();
-					}
-				}
-
 				// Fully pad all unused input connections of this box cell with S0
 				// Fully pad all undriven output connections of this box cell with anonymous wires
 				// NB: Assume box_module->ports are sorted alphabetically
@@ -388,11 +346,11 @@ struct XAigerWriter
 						RTLIL::SigSpec rhs;
 						if (it != cell->connections_.end()) {
 							if (GetSize(it->second) < GetSize(w))
-								it->second.append(RTLIL::SigSpec(RTLIL::S0, GetSize(w)-GetSize(it->second)));
+								it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
 							rhs = it->second;
 						}
 						else {
-							rhs = RTLIL::SigSpec(RTLIL::S0, GetSize(w));
+							rhs = RTLIL::SigSpec(State::S0, GetSize(w));
 							cell->setPort(port_name, rhs);
 						}
 
@@ -400,10 +358,10 @@ struct XAigerWriter
 						for (auto b : rhs.bits()) {
 							SigBit I = sigmap(b);
 							if (b == RTLIL::Sx)
-								b = RTLIL::S0;
+								b = State::S0;
 							else if (I != b) {
 								if (I == RTLIL::Sx)
-									alias_map[b] = RTLIL::S0;
+									alias_map[b] = State::S0;
 								else
 									alias_map[b] = I;
 							}
@@ -671,7 +629,7 @@ struct XAigerWriter
 							if (holes_cell)
 								port_wire.append(holes_wire);
 							else
-								holes_module->connect(holes_wire, RTLIL::S0);
+								holes_module->connect(holes_wire, State::S0);
 						}
 						if (!port_wire.empty())
 							holes_cell->setPort(w->name, port_wire);