1 files changed, 56 insertions, 217 deletions

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index e7d767721..830c86787 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -78,7 +78,7 @@ struct XAigerWriter
 	Module *module;
 	SigMap sigmap;
 
-	pool<SigBit> input_bits, output_bits, external_bits;
+	pool<SigBit> input_bits, output_bits;
 	dict<SigBit, SigBit> not_map, alias_map;
 	dict<SigBit, pair<SigBit, SigBit>> and_map;
 	vector<SigBit> ci_bits, co_bits;
@@ -136,7 +136,7 @@ struct XAigerWriter
 		return a;
 	}
 
-	XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
+	XAigerWriter(Module *module) : module(module), sigmap(module)
 	{
 		pool<SigBit> undriven_bits;
 		pool<SigBit> unused_bits;
@@ -166,9 +166,7 @@ struct XAigerWriter
 				if (bit.wire == nullptr) {
 					if (wire->port_output) {
 						aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
-						if (holes_mode)
-							output_bits.insert(wirebit);
-						//external_bits.insert(wirebit);
+						output_bits.insert(wirebit);
 					}
 					continue;
 				}
@@ -182,10 +180,7 @@ struct XAigerWriter
 				if (wire->port_output) {
 					if (bit != wirebit)
 						alias_map[wirebit] = bit;
-					if (holes_mode)
-						output_bits.insert(wirebit);
-					else
-						external_bits.insert(wirebit);
+					output_bits.insert(wirebit);
 				}
 
 				if (wire->port_input && wire->port_output)
@@ -207,11 +202,9 @@ struct XAigerWriter
 				unused_bits.erase(A);
 				undriven_bits.erase(Y);
 				not_map[Y] = A;
-				if (!holes_mode) {
-					toposort.node(cell->name);
-					bit_users[A].insert(cell->name);
-					bit_drivers[Y].insert(cell->name);
-				}
+				toposort.node(cell->name);
+				bit_users[A].insert(cell->name);
+				bit_drivers[Y].insert(cell->name);
 				continue;
 			}
 
@@ -224,17 +217,13 @@ struct XAigerWriter
 				unused_bits.erase(B);
 				undriven_bits.erase(Y);
 				and_map[Y] = make_pair(A, B);
-				if (!holes_mode) {
-					toposort.node(cell->name);
-					bit_users[A].insert(cell->name);
-					bit_users[B].insert(cell->name);
-					bit_drivers[Y].insert(cell->name);
-				}
+				toposort.node(cell->name);
+				bit_users[A].insert(cell->name);
+				bit_users[B].insert(cell->name);
+				bit_drivers[Y].insert(cell->name);
 				continue;
 			}
 
-			log_assert(!holes_mode);
-
 			if (cell->type == "$__ABC9_FF_")
 			{
 				SigBit D = sigmap(cell->getPort("\\D").as_bit());
@@ -298,7 +287,7 @@ struct XAigerWriter
 				if (!is_input && !is_output)
 					log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
 
-				if (is_input) {
+				if (is_input)
 					for (auto b : c.second) {
 						Wire *w = b.wire;
 						if (!w) continue;
@@ -306,13 +295,19 @@ struct XAigerWriter
 							SigBit I = sigmap(b);
 							if (I != b)
 								alias_map[b] = I;
-							if (holes_mode)
-								output_bits.insert(b);
-							else
-								external_bits.insert(b);
+							output_bits.insert(b);
 						}
 					}
-				}
+
+				if (is_output)
+					for (auto b : c.second) {
+						Wire *w = b.wire;
+						if (!w) continue;
+						SigBit O = sigmap(b);
+						if (O != b)
+							alias_map[O] = b;
+						input_bits.insert(O);
+					}
 			}
 
 			//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
@@ -495,57 +490,27 @@ struct XAigerWriter
 			// TODO: Free memory from toposort, bit_drivers, bit_users
 		}
 
-		if (!holes_mode)
-			for (auto cell : module->cells())
-				if (!module->selected(cell))
-					for (auto &conn : cell->connections())
-						if (cell->input(conn.first))
-							for (auto wirebit : conn.second)
-								if (sigmap(wirebit).wire)
-									external_bits.insert(wirebit);
-
-		// For all bits consumed outside of the selected cells,
-		//   but driven from a selected cell, then add it as
-		//   a primary output
-		for (auto wirebit : external_bits) {
-			SigBit bit = sigmap(wirebit);
-			if (!bit.wire)
-				continue;
-			if (!undriven_bits.count(bit)) {
-				if (bit != wirebit)
-					alias_map[wirebit] = bit;
-				output_bits.insert(wirebit);
-			}
-		}
-
 		for (auto bit : input_bits)
-			undriven_bits.erase(sigmap(bit));
+			undriven_bits.erase(bit);
 		for (auto bit : output_bits)
 			unused_bits.erase(sigmap(bit));
 		for (auto bit : unused_bits)
 			undriven_bits.erase(bit);
-
-		// Make all undriven bits a primary input
-		if (!holes_mode)
+		if (!undriven_bits.empty()) {
 			for (auto bit : undriven_bits) {
+				log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
 				input_bits.insert(bit);
-				undriven_bits.erase(bit);
 			}
-
-		if (holes_mode) {
-			struct sort_by_port_id {
-				bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
-					return a.wire->port_id < b.wire->port_id;
-				}
-			};
-			input_bits.sort(sort_by_port_id());
-			output_bits.sort(sort_by_port_id());
-		}
-		else {
-			input_bits.sort();
-			output_bits.sort();
+			log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
 		}
 
+		struct sort_by_port_id {
+			bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
+				return a.wire->port_id < b.wire->port_id;
+			}
+		};
+		input_bits.sort(sort_by_port_id());
+		output_bits.sort(sort_by_port_id());
 		not_map.sort();
 		and_map.sort();
 
@@ -680,101 +645,29 @@ struct XAigerWriter
 		//	write_o_buffer(0);
 
 		if (!box_list.empty() || !ff_bits.empty()) {
-			RTLIL::Module *holes_module = module->design->addModule("$__holes__");
-			log_assert(holes_module);
-
-			dict<IdString, Cell*> cell_cache;
-
-			int port_id = 1;
 			int box_count = 0;
 			for (auto cell : box_list) {
 				RTLIL::Module* orig_box_module = module->design->module(cell->type);
 				log_assert(orig_box_module);
 				IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
 				RTLIL::Module* box_module = module->design->module(derived_name);
-				if (box_module->has_processes())
-					Pass::call_on_module(module->design, box_module, "proc");
 
 				int box_inputs = 0, box_outputs = 0;
-				auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
-				Cell *holes_cell = r.first->second;
-				if (r.second && box_module->get_bool_attribute("\\whitebox")) {
-					holes_cell = holes_module->addCell(cell->name, cell->type);
-					holes_cell->parameters = cell->parameters;
-					r.first->second = holes_cell;
-
-					// Since Module::derive() will create a new module, there
-					//   is a chance that the ports will be alphabetically ordered
-					//   again, which is a problem when carry-chains are involved.
-					//   Inherit the port ordering from the original module here...
-					//   (and set the port_id below, when iterating through those)
-					log_assert(GetSize(box_module->ports) == GetSize(orig_box_module->ports));
-					box_module->ports = orig_box_module->ports;
-				}
-
 				// NB: Assume box_module->ports are sorted alphabetically
 				//     (as RTLIL::Module::fixup_ports() would do)
-				int box_port_id = 1;
 				for (const auto &port_name : box_module->ports) {
 					RTLIL::Wire *w = box_module->wire(port_name);
 					log_assert(w);
-					if (r.second)
-						w->port_id = box_port_id++;
-					RTLIL::Wire *holes_wire;
-					RTLIL::SigSpec port_sig;
 					if (w->port_input)
-						for (int i = 0; i < GetSize(w); i++) {
-							box_inputs++;
-							holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
-							if (!holes_wire) {
-								holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
-								holes_wire->port_input = true;
-								holes_wire->port_id = port_id++;
-								holes_module->ports.push_back(holes_wire->name);
-							}
-							if (holes_cell)
-								port_sig.append(holes_wire);
-						}
-					if (w->port_output) {
+						box_inputs += GetSize(w);
+					if (w->port_output)
 						box_outputs += GetSize(w);
-						for (int i = 0; i < GetSize(w); i++) {
-							if (GetSize(w) == 1)
-								holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
-							else
-								holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
-							holes_wire->port_output = true;
-							holes_wire->port_id = port_id++;
-							holes_module->ports.push_back(holes_wire->name);
-							if (holes_cell)
-								port_sig.append(holes_wire);
-							else
-								holes_module->connect(holes_wire, State::S0);
-						}
-					}
-					if (!port_sig.empty()) {
-						if (r.second)
-							holes_cell->setPort(w->name, port_sig);
-						else
-							holes_module->connect(holes_cell->getPort(w->name), port_sig);
-					}
 				}
 
 				// For flops only, create an extra 1-bit input that drives a new wire
 				//   called "<cell>.$abc9_currQ" that is used below
-				if (box_module->get_bool_attribute("\\abc9_flop")) {
-					log_assert(holes_cell);
-
+				if (box_module->get_bool_attribute("\\abc9_flop"))
 					box_inputs++;
-					Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
-					if (!holes_wire) {
-						holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
-						holes_wire->port_input = true;
-						holes_wire->port_id = port_id++;
-						holes_module->ports.push_back(holes_wire->name);
-					}
-					Wire *w = holes_module->addWire(stringf("%s.$abc9_currQ", cell->name.c_str()));
-					holes_module->connect(w, holes_wire);
-				}
 
 				write_h_buffer(box_inputs);
 				write_h_buffer(box_outputs);
@@ -814,81 +707,27 @@ struct XAigerWriter
 			f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
 			f.write(buffer_str.data(), buffer_str.size());
 
-			if (holes_module) {
-				log_push();
-
-				// NB: fixup_ports() will sort ports by name
-				//holes_module->fixup_ports();
-				holes_module->check();
-
-				// Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
-				//   since boxes may contain parameters in which case `flatten` would have
-				//   created a new $paramod ...
-				Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
-
-				dict<SigSig, SigSig> replace;
-				for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
-					auto cell = it->second;
-					if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
-								"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
-						SigBit D = cell->getPort("\\D");
-						SigBit Q = cell->getPort("\\Q");
-						// Remove the DFF cell from what needs to be a combinatorial box
-						it = holes_module->cells_.erase(it);
-						Wire *port;
-						if (GetSize(Q.wire) == 1)
-							port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
-						else
-							port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
-						log_assert(port);
-						// Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
-						//   in order to extract the combinatorial control logic that feeds the box
-						//   (i.e. clock enable, synchronous reset, etc.)
-						replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
-						// Since `flatten` above would have created wires named "<cell>.Q",
-						//   extract the pre-techmap cell name
-						auto pos = Q.wire->name.str().rfind(".");
-						log_assert(pos != std::string::npos);
-						IdString driver = Q.wire->name.substr(0, pos);
-						// And drive the signal that was previously driven by "DFF.Q" (typically
-						//   used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
-						//   wire (which itself is driven an input port) we inserted above
-						Wire *currQ = holes_module->wire(stringf("%s.$abc9_currQ", driver.c_str()));
-						log_assert(currQ);
-						holes_module->connect(Q, currQ);
-						continue;
-					}
-					else if (!cell->type.in("$_NOT_", "$_AND_"))
-						log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
-					++it;
-				}
+			RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
+			log_assert(holes_module);
 
-				for (auto &conn : holes_module->connections_) {
-					auto it = replace.find(conn);
-					if (it != replace.end())
-						conn = it->second;
-				}
+			for (auto cell : holes_module->cells())
+				if (!cell->type.in("$_NOT_", "$_AND_"))
+					log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
 
-				// Move into a new (temporary) design so that "clean" will only
-				// operate (and run checks on) this one module
-				RTLIL::Design *holes_design = new RTLIL::Design;
-				module->design->modules_.erase(holes_module->name);
-				holes_design->add(holes_module);
-				Pass::call(holes_design, "opt -purge");
-
-				std::stringstream a_buffer;
-				XAigerWriter writer(holes_module, true /* holes_mode */);
-				writer.write_aiger(a_buffer, false /*ascii_mode*/);
-				delete holes_design;
-
-				f << "a";
-				std::string buffer_str = a_buffer.str();
-				int32_t buffer_size_be = to_big_endian(buffer_str.size());
-				f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
-				f.write(buffer_str.data(), buffer_str.size());
-
-				log_pop();
-			}
+			module->design->selection_stack.emplace_back(false);
+			module->design->selection().select(holes_module);
+
+			std::stringstream a_buffer;
+			XAigerWriter writer(holes_module);
+			writer.write_aiger(a_buffer, false /*ascii_mode*/);
+
+			module->design->selection_stack.pop_back();
+
+			f << "a";
+			buffer_str = a_buffer.str();
+			buffer_size_be = to_big_endian(buffer_str.size());
+			f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
+			f.write(buffer_str.data(), buffer_str.size());
 		}
 
 		f << "h";