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-rw-r--r--backends/aiger/xaiger.cc387
1 files changed, 93 insertions, 294 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 05e9678ee..c01adde3d 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -185,13 +185,7 @@ struct XAigerWriter
}
}
- // TODO: Speed up toposort -- ultimately we care about
- // box ordering, but not individual AIG cells
- dict<SigBit, pool<IdString>> bit_drivers, bit_users;
- TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
- bool abc9_box_seen = false;
-
- for (auto cell : module->selected_cells()) {
+ for (auto cell : module->cells()) {
if (cell->type == "$_NOT_")
{
SigBit A = sigmap(cell->getPort("\\A").as_bit());
@@ -199,9 +193,6 @@ struct XAigerWriter
unused_bits.erase(A);
undriven_bits.erase(Y);
not_map[Y] = A;
- toposort.node(cell->name);
- bit_users[A].insert(cell->name);
- bit_drivers[Y].insert(cell->name);
continue;
}
@@ -214,10 +205,6 @@ struct XAigerWriter
unused_bits.erase(B);
undriven_bits.erase(Y);
and_map[Y] = make_pair(A, B);
- toposort.node(cell->name);
- bit_users[A].insert(cell->name);
- bit_users[B].insert(cell->name);
- bit_drivers[Y].insert(cell->name);
continue;
}
@@ -238,27 +225,18 @@ struct XAigerWriter
RTLIL::Module* inst_module = module->design->module(cell->type);
if (inst_module) {
- bool abc9_box = inst_module->attributes.count("\\abc9_box_id");
- bool abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
- if (abc9_box && cell->get_bool_attribute("\\abc9_keep"))
- abc9_box = false;
+ auto it = cell->attributes.find("\\abc9_box_seq");
+ if (it != cell->attributes.end()) {
+ int abc9_box_seq = it->second.as_int();
+ if (GetSize(box_list) <= abc9_box_seq)
+ box_list.resize(abc9_box_seq+1);
+ box_list[abc9_box_seq] = cell;
+ if (!inst_module->get_bool_attribute("\\abc9_flop"))
+ continue;
+ }
for (const auto &conn : cell->connections()) {
auto port_wire = inst_module->wire(conn.first);
-
- if (abc9_box) {
- // Ignore inout for the sake of topographical ordering
- if (port_wire->port_input && !port_wire->port_output)
- for (auto bit : sigmap(conn.second))
- bit_users[bit].insert(cell->name);
- if (port_wire->port_output)
- for (auto bit : sigmap(conn.second))
- bit_drivers[bit].insert(cell->name);
-
- if (!abc9_flop)
- continue;
- }
-
if (port_wire->port_output) {
int arrival = 0;
auto it = port_wire->attributes.find("\\abc9_arrival");
@@ -272,12 +250,6 @@ struct XAigerWriter
arrival_times[bit] = arrival;
}
}
-
- if (abc9_box) {
- abc9_box_seen = true;
- toposort.node(cell->name);
- continue;
- }
}
bool cell_known = inst_module || cell->known();
@@ -305,138 +277,55 @@ struct XAigerWriter
//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
}
- if (abc9_box_seen) {
- for (auto &it : bit_users)
- if (bit_drivers.count(it.first))
- for (auto driver_cell : bit_drivers.at(it.first))
- for (auto user_cell : it.second)
- toposort.edge(driver_cell, user_cell);
-
-#if 0
- toposort.analyze_loops = true;
-#endif
- bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
-#if 0
- unsigned i = 0;
- for (auto &it : toposort.loops) {
- log(" loop %d\n", i++);
- for (auto cell_name : it) {
- auto cell = module->cell(cell_name);
- log_assert(cell);
- log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
- }
- }
-#endif
- log_assert(no_loops);
-
- for (auto cell_name : toposort.sorted) {
- RTLIL::Cell *cell = module->cell(cell_name);
- log_assert(cell);
+ for (auto cell : box_list) {
+ log_assert(cell);
- RTLIL::Module* box_module = module->design->module(cell->type);
- if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
- continue;
-
- bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
-
- auto r = box_ports.insert(cell->type);
- if (r.second) {
- // Make carry in the last PI, and carry out the last PO
- // since ABC requires it this way
- IdString carry_in, carry_out;
- for (const auto &port_name : box_module->ports) {
- auto w = box_module->wire(port_name);
- log_assert(w);
- if (w->get_bool_attribute("\\abc9_carry")) {
- if (w->port_input) {
- if (carry_in != IdString())
- log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
- carry_in = port_name;
- }
- if (w->port_output) {
- if (carry_out != IdString())
- log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
- carry_out = port_name;
- }
- }
- else
- r.first->second.push_back(port_name);
- }
-
- if (carry_in != IdString() && carry_out == IdString())
- log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
- if (carry_in == IdString() && carry_out != IdString())
- log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
- if (carry_in != IdString()) {
- r.first->second.push_back(carry_in);
- r.first->second.push_back(carry_out);
- }
- }
+ RTLIL::Module* box_module = module->design->module(cell->type);
+ log_assert(box_module);
+ log_assert(box_module->attributes.count("\\abc9_box_id"));
- // Fully pad all unused input connections of this box cell with S0
- // Fully pad all undriven output connections of this box cell with anonymous wires
- for (auto port_name : r.first->second) {
+ auto r = box_ports.insert(cell->type);
+ if (r.second) {
+ // Make carry in the last PI, and carry out the last PO
+ // since ABC requires it this way
+ IdString carry_in, carry_out;
+ for (const auto &port_name : box_module->ports) {
auto w = box_module->wire(port_name);
log_assert(w);
- auto it = cell->connections_.find(port_name);
- if (w->port_input) {
- RTLIL::SigSpec rhs;
- if (it != cell->connections_.end()) {
- if (GetSize(it->second) < GetSize(w))
- it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
- rhs = it->second;
+ if (w->get_bool_attribute("\\abc9_carry")) {
+ if (w->port_input) {
+ if (carry_in != IdString())
+ log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
+ carry_in = port_name;
}
- else {
- rhs = RTLIL::SigSpec(State::S0, GetSize(w));
- cell->setPort(port_name, rhs);
- }
-
- for (auto b : rhs) {
- SigBit I = sigmap(b);
- if (b == RTLIL::Sx)
- b = State::S0;
- else if (I != b) {
- if (I == RTLIL::Sx)
- alias_map[b] = State::S0;
- else
- alias_map[b] = I;
- }
- co_bits.emplace_back(b);
- unused_bits.erase(I);
+ if (w->port_output) {
+ if (carry_out != IdString())
+ log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
+ carry_out = port_name;
}
}
- if (w->port_output) {
- RTLIL::SigSpec rhs;
- auto it = cell->connections_.find(w->name);
- if (it != cell->connections_.end()) {
- if (GetSize(it->second) < GetSize(w))
- it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
- rhs = it->second;
- }
- else {
- Wire *wire = module->addWire(NEW_ID, GetSize(w));
- if (blackbox)
- wire->set_bool_attribute(ID(abc9_padding));
- rhs = wire;
- cell->setPort(port_name, rhs);
- }
+ else
+ r.first->second.push_back(port_name);
+ }
- for (const auto &b : rhs.bits()) {
- SigBit O = sigmap(b);
- if (O != b)
- alias_map[O] = b;
- ci_bits.emplace_back(b);
- undriven_bits.erase(O);
- }
- }
+ if (carry_in != IdString() && carry_out == IdString())
+ log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
+ if (carry_in == IdString() && carry_out != IdString())
+ log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
+ if (carry_in != IdString()) {
+ r.first->second.push_back(carry_in);
+ r.first->second.push_back(carry_out);
}
+ }
- // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
- if (box_module->get_bool_attribute("\\abc9_flop")) {
- SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
- if (rhs.empty())
- log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
+ for (auto port_name : r.first->second) {
+ auto w = box_module->wire(port_name);
+ log_assert(w);
+ SigSpec rhs = cell->connections_.at(port_name, SigSpec());
+ if (w->port_input) {
+ // Add padding to fill entire port
+ rhs.append(SigSpec(State::Sx, GetSize(w)-GetSize(rhs)));
for (auto b : rhs) {
SigBit I = sigmap(b);
if (b == RTLIL::Sx)
@@ -451,11 +340,39 @@ struct XAigerWriter
unused_bits.erase(I);
}
}
-
- box_list.emplace_back(cell);
+ if (w->port_output) {
+ // Add padding to fill entire port
+ rhs.append(SigSpec(State::Sx, GetSize(w)-GetSize(rhs)));
+ for (const auto &b : rhs) {
+ SigBit O = sigmap(b);
+ if (O != b)
+ alias_map[O] = b;
+ ci_bits.emplace_back(b);
+ undriven_bits.erase(O);
+ }
+ }
}
- // TODO: Free memory from toposort, bit_drivers, bit_users
+ // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
+ if (box_module->get_bool_attribute("\\abc9_flop")) {
+ SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
+ if (rhs.empty())
+ log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
+
+ for (auto b : rhs) {
+ SigBit I = sigmap(b);
+ if (b == RTLIL::Sx)
+ b = State::S0;
+ else if (I != b) {
+ if (I == RTLIL::Sx)
+ alias_map[b] = State::S0;
+ else
+ alias_map[b] = I;
+ }
+ co_bits.emplace_back(b);
+ unused_bits.erase(I);
+ }
+ }
}
for (auto bit : input_bits)
@@ -500,8 +417,11 @@ struct XAigerWriter
for (auto &bit : ci_bits) {
aig_m++, aig_i++;
- log_assert(!aig_map.count(bit));
- aig_map[bit] = 2*aig_m;
+ // State::Sx if padding
+ if (bit != State::Sx) {
+ log_assert(!aig_map.count(bit));
+ aig_map[bit] = 2*aig_m;
+ }
}
for (auto bit : co_bits) {
@@ -611,89 +531,32 @@ struct XAigerWriter
// write_o_buffer(0);
if (!box_list.empty() || !ff_bits.empty()) {
- RTLIL::Module *holes_module = module->design->addModule("$__holes__");
+ RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
log_assert(holes_module);
dict<IdString, Cell*> cell_cache;
- int port_id = 1;
int box_count = 0;
for (auto cell : box_list) {
- RTLIL::Module* orig_box_module = module->design->module(cell->type);
- log_assert(orig_box_module);
- IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
- RTLIL::Module* box_module = module->design->module(derived_name);
- if (box_module->has_processes())
- Pass::call_on_module(module->design, box_module, "proc");
-
- auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
- Cell *holes_cell = r.first->second;
- if (r.second && box_module->get_bool_attribute("\\whitebox")) {
- holes_cell = holes_module->addCell(cell->name, cell->type);
- holes_cell->parameters = cell->parameters;
- r.first->second = holes_cell;
- }
+ log_assert(cell);
+
+ RTLIL::Module* box_module = module->design->module(cell->type);
+ log_assert(box_module);
int box_inputs = 0, box_outputs = 0;
- for (auto port_name : box_ports.at(cell->type)) {
+ for (auto port_name : box_module->ports) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);
- RTLIL::Wire *holes_wire;
- RTLIL::SigSpec port_sig;
-
if (w->port_input)
- for (int i = 0; i < GetSize(w); i++) {
- box_inputs++;
- holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
- if (!holes_wire) {
- holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
- holes_wire->port_input = true;
- holes_wire->port_id = port_id++;
- holes_module->ports.push_back(holes_wire->name);
- }
- if (holes_cell)
- port_sig.append(holes_wire);
- }
- if (w->port_output) {
+ box_inputs += GetSize(w);
+ if (w->port_output)
box_outputs += GetSize(w);
- for (int i = 0; i < GetSize(w); i++) {
- if (GetSize(w) == 1)
- holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
- else
- holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
- holes_wire->port_output = true;
- holes_wire->port_id = port_id++;
- holes_module->ports.push_back(holes_wire->name);
- if (holes_cell)
- port_sig.append(holes_wire);
- else
- holes_module->connect(holes_wire, State::S0);
- }
- }
- if (!port_sig.empty()) {
- if (r.second)
- holes_cell->setPort(w->name, port_sig);
- else
- holes_module->connect(holes_cell->getPort(w->name), port_sig);
- }
}
// For flops only, create an extra 1-bit input that drives a new wire
// called "<cell>.abc9_ff.Q" that is used below
- if (box_module->get_bool_attribute("\\abc9_flop")) {
- log_assert(holes_cell);
-
+ if (box_module->get_bool_attribute("\\abc9_flop"))
box_inputs++;
- Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
- if (!holes_wire) {
- holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
- holes_wire->port_input = true;
- holes_wire->port_id = port_id++;
- holes_module->ports.push_back(holes_wire->name);
- }
- Wire *w = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
- holes_module->connect(w, holes_wire);
- }
write_h_buffer(box_inputs);
write_h_buffer(box_outputs);
@@ -746,79 +609,15 @@ struct XAigerWriter
f.write(buffer_str.data(), buffer_str.size());
if (holes_module) {
- log_push();
-
- // NB: fixup_ports() will sort ports by name
- //holes_module->fixup_ports();
- holes_module->check();
-
- // Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
- // since boxes may contain parameters in which case `flatten` would have
- // created a new $paramod ...
- Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
-
- dict<SigSig, SigSig> replace;
- for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
- auto cell = it->second;
- if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
- "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
- SigBit D = cell->getPort("\\D");
- SigBit Q = cell->getPort("\\Q");
- // Remove the DFF cell from what needs to be a combinatorial box
- it = holes_module->cells_.erase(it);
- Wire *port;
- if (GetSize(Q.wire) == 1)
- port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
- else
- port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
- log_assert(port);
- // Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
- // in order to extract the combinatorial control logic that feeds the box
- // (i.e. clock enable, synchronous reset, etc.)
- replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
- // Since `flatten` above would have created wires named "<cell>.Q",
- // extract the pre-techmap cell name
- auto pos = Q.wire->name.str().rfind(".");
- log_assert(pos != std::string::npos);
- IdString driver = Q.wire->name.substr(0, pos);
- // And drive the signal that was previously driven by "DFF.Q" (typically
- // used to implement clock-enable functionality) with the "<cell>.abc9_ff.Q"
- // wire (which itself is driven an input port) we inserted above
- Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
- log_assert(currQ);
- holes_module->connect(Q, currQ);
- continue;
- }
- else if (!cell->type.in("$_NOT_", "$_AND_"))
- log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
- ++it;
- }
-
- for (auto &conn : holes_module->connections_) {
- auto it = replace.find(conn);
- if (it != replace.end())
- conn = it->second;
- }
-
- // Move into a new (temporary) design so that "clean" will only
- // operate (and run checks on) this one module
- RTLIL::Design *holes_design = new RTLIL::Design;
- module->design->modules_.erase(holes_module->name);
- holes_design->add(holes_module);
- Pass::call(holes_design, "opt -purge");
-
std::stringstream a_buffer;
XAigerWriter writer(holes_module, true /* holes_mode */);
writer.write_aiger(a_buffer, false /*ascii_mode*/);
- delete holes_design;
f << "a";
std::string buffer_str = a_buffer.str();
int32_t buffer_size_be = to_big_endian(buffer_str.size());
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
f.write(buffer_str.data(), buffer_str.size());
-
- log_pop();
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 02:47:13 +0000