diff options
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 | ||||
| -rw-r--r-- | backends/json/json.cc | 6 | ||||
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 12 |
3 files changed, 14 insertions, 6 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 76b7efbfc..3cf36aca8 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -650,7 +650,7 @@ struct XAigerWriter log_assert(mergeability > 0); write_r_buffer(mergeability); - Const init = cell->attributes.at(ID(abc9_init)); + Const init = cell->attributes.at(ID(abc9_init), State::Sx); log_assert(GetSize(init) == 1); if (init == State::S1) write_s_buffer(1); diff --git a/backends/json/json.cc b/backends/json/json.cc index 5c67cb857..6c924ff99 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -104,7 +104,7 @@ struct JsonWriter if (state < 2) str += " "; f << get_string(str); - } else if (compat_int_mode && GetSize(value) == 32 && value.is_fully_def()) { + } else if (compat_int_mode && GetSize(value) <= 32 && value.is_fully_def()) { if ((value.flags & RTLIL::ConstFlags::CONST_FLAG_SIGNED) != 0) f << stringf("%d", value.as_int()); else @@ -296,7 +296,7 @@ struct JsonBackend : public Backend { log(" include AIG models for the different gate types\n"); log("\n"); log(" -compat-int\n"); - log(" emit 32-bit fully-defined parameter values directly\n"); + log(" emit 32-bit or smaller fully-defined parameter values directly\n"); log(" as JSON numbers (for compatibility with old parsers)\n"); log("\n"); log("\n"); @@ -540,7 +540,7 @@ struct JsonPass : public Pass { log(" also include AIG models for the different gate types\n"); log("\n"); log(" -compat-int\n"); - log(" emit 32-bit fully-defined parameter values directly\n"); + log(" emit 32-bit or smaller fully-defined parameter values directly\n"); log(" as JSON numbers (for compatibility with old parsers)\n"); log("\n"); log("See 'help write_json' for a description of the JSON format used.\n"); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 682c47a1f..19541f1c4 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1417,11 +1417,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) decimal = 1; f << ", "; - dump_const(f, cell->getParam("\\T_LIMIT")); + dump_const(f, cell->getParam("\\T_LIMIT_MIN")); + f << ": "; + dump_const(f, cell->getParam("\\T_LIMIT_TYP")); + f << ": "; + dump_const(f, cell->getParam("\\T_LIMIT_MAX")); if (spec_type == "$setuphold" || spec_type == "$recrem" || spec_type == "$fullskew") { f << ", "; - dump_const(f, cell->getParam("\\T_LIMIT2")); + dump_const(f, cell->getParam("\\T_LIMIT2_MIN")); + f << ": "; + dump_const(f, cell->getParam("\\T_LIMIT2_TYP")); + f << ": "; + dump_const(f, cell->getParam("\\T_LIMIT2_MAX")); } f << ");\n"; |