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-rw-r--r--backends/cxxrtl/cxxrtl.cc1305
-rw-r--r--backends/cxxrtl/cxxrtl.h67
-rw-r--r--backends/edif/edif.cc122
-rw-r--r--backends/firrtl/firrtl.cc13
-rw-r--r--backends/ilang/ilang_backend.cc12
-rw-r--r--backends/json/json.cc10
6 files changed, 1155 insertions, 374 deletions
diff --git a/backends/cxxrtl/cxxrtl.cc b/backends/cxxrtl/cxxrtl.cc
index d1a855bf0..237700b29 100644
--- a/backends/cxxrtl/cxxrtl.cc
+++ b/backends/cxxrtl/cxxrtl.cc
@@ -171,14 +171,19 @@ struct Scheduler {
}
};
-static bool is_unary_cell(RTLIL::IdString type)
+bool is_input_wire(const RTLIL::Wire *wire)
+{
+ return wire->port_input && !wire->port_output;
+}
+
+bool is_unary_cell(RTLIL::IdString type)
{
return type.in(
ID($not), ID($logic_not), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
ID($pos), ID($neg));
}
-static bool is_binary_cell(RTLIL::IdString type)
+bool is_binary_cell(RTLIL::IdString type)
{
return type.in(
ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or),
@@ -187,34 +192,77 @@ static bool is_binary_cell(RTLIL::IdString type)
ID($add), ID($sub), ID($mul), ID($div), ID($mod));
}
-static bool is_elidable_cell(RTLIL::IdString type)
+bool is_elidable_cell(RTLIL::IdString type)
{
return is_unary_cell(type) || is_binary_cell(type) || type.in(
ID($mux), ID($concat), ID($slice));
}
-static bool is_sync_ff_cell(RTLIL::IdString type)
+bool is_sync_ff_cell(RTLIL::IdString type)
{
return type.in(
ID($dff), ID($dffe));
}
-static bool is_ff_cell(RTLIL::IdString type)
+bool is_ff_cell(RTLIL::IdString type)
{
return is_sync_ff_cell(type) || type.in(
ID($adff), ID($dffsr), ID($dlatch), ID($dlatchsr), ID($sr));
}
-static bool is_internal_cell(RTLIL::IdString type)
+bool is_internal_cell(RTLIL::IdString type)
{
return type[0] == '$' && !type.begins_with("$paramod\\");
}
+bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
+{
+ RTLIL::Module *cell_module = cell->module->design->module(cell->type);
+ log_assert(cell_module != nullptr);
+ return cell_module->get_bool_attribute(ID(cxxrtl.blackbox));
+}
+
+enum class CxxrtlPortType {
+ UNKNOWN = 0, // or mixed comb/sync
+ COMB = 1,
+ SYNC = 2,
+};
+
+CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
+{
+ RTLIL::Module *cell_module = cell->module->design->module(cell->type);
+ if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl.blackbox)))
+ return CxxrtlPortType::UNKNOWN;
+ RTLIL::Wire *cell_output_wire = cell_module->wire(port);
+ log_assert(cell_output_wire != nullptr);
+ bool is_comb = cell_output_wire->get_bool_attribute(ID(cxxrtl.comb));
+ bool is_sync = cell_output_wire->get_bool_attribute(ID(cxxrtl.sync));
+ if (is_comb && is_sync)
+ log_cmd_error("Port `%s.%s' is marked as both `cxxrtl.comb` and `cxxrtl.sync`.\n",
+ log_id(cell_module), log_signal(cell_output_wire));
+ else if (is_comb)
+ return CxxrtlPortType::COMB;
+ else if (is_sync)
+ return CxxrtlPortType::SYNC;
+ return CxxrtlPortType::UNKNOWN;
+}
+
+bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port)
+{
+ return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB;
+}
+
+bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, RTLIL::IdString port)
+{
+ return cxxrtl_port_type(cell, port) == CxxrtlPortType::SYNC;
+}
+
struct FlowGraph {
struct Node {
enum class Type {
CONNECT,
- CELL,
+ CELL_SYNC,
+ CELL_EVAL,
PROCESS
};
@@ -225,7 +273,7 @@ struct FlowGraph {
};
std::vector<Node*> nodes;
- dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_defs, wire_uses;
+ dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_comb_defs, wire_sync_defs, wire_uses;
dict<const RTLIL::Wire*, bool> wire_def_elidable, wire_use_elidable;
~FlowGraph()
@@ -234,13 +282,17 @@ struct FlowGraph {
delete node;
}
- void add_defs(Node *node, const RTLIL::SigSpec &sig, bool elidable)
+ void add_defs(Node *node, const RTLIL::SigSpec &sig, bool fully_sync, bool elidable)
{
for (auto chunk : sig.chunks())
- if (chunk.wire)
- wire_defs[chunk.wire].insert(node);
- // Only defs of an entire wire in the right order can be elided.
- if (sig.is_wire())
+ if (chunk.wire) {
+ if (fully_sync)
+ wire_sync_defs[chunk.wire].insert(node);
+ else
+ wire_comb_defs[chunk.wire].insert(node);
+ }
+ // Only comb defs of an entire wire in the right order can be elided.
+ if (!fully_sync && sig.is_wire())
wire_def_elidable[sig.as_wire()] = elidable;
}
@@ -268,7 +320,7 @@ struct FlowGraph {
// Connections
void add_connect_defs_uses(Node *node, const RTLIL::SigSig &conn)
{
- add_defs(node, conn.first, /*elidable=*/true);
+ add_defs(node, conn.first, /*fully_sync=*/false, /*elidable=*/true);
add_uses(node, conn.second);
}
@@ -283,21 +335,59 @@ struct FlowGraph {
}
// Cells
- void add_cell_defs_uses(Node *node, const RTLIL::Cell *cell)
+ void add_cell_sync_defs(Node *node, const RTLIL::Cell *cell)
+ {
+ // To understand why this node type is necessary and why it produces comb defs, consider a cell
+ // with input \i and sync output \o, used in a design such that \i is connected to \o. This does
+ // not result in a feedback arc because the output is synchronous. However, a naive implementation
+ // of code generation for cells that assigns to inputs, evaluates cells, assigns from outputs
+ // would not be able to immediately converge...
+ //
+ // wire<1> i_tmp;
+ // cell->p_i = i_tmp.curr;
+ // cell->eval();
+ // i_tmp.next = cell->p_o.curr;
+ //
+ // ... since the wire connecting the input and output ports would not be localizable. To solve
+ // this, the cell is split into two scheduling nodes; one exclusively for sync outputs, and
+ // another for inputs and all non-sync outputs. This way the generated code can be rearranged...
+ //
+ // value<1> i_tmp;
+ // i_tmp = cell->p_o.curr;
+ // cell->p_i = i_tmp;
+ // cell->eval();
+ //
+ // eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of
+ // connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not
+ // as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have a sync def,
+ // and this node would be an ordinary CONNECT node, with `\lhs` having a comb def. Because it isn't,
+ // a special node type is used, the right-hand side does not appear anywhere, and the left-hand
+ // side has a comb def.
+ for (auto conn : cell->connections())
+ if (cell->output(conn.first))
+ if (is_cxxrtl_sync_port(cell, conn.first)) {
+ // See note regarding elidability below.
+ add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
+ }
+ }
+
+ void add_cell_eval_defs_uses(Node *node, const RTLIL::Cell *cell)
{
- log_assert(cell->known());
for (auto conn : cell->connections()) {
if (cell->output(conn.first)) {
- if (is_sync_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID(CLK_ENABLE)).as_bool()))
- /* non-combinatorial outputs do not introduce defs */;
- else if (is_elidable_cell(cell->type))
- add_defs(node, conn.second, /*elidable=*/true);
+ if (is_elidable_cell(cell->type))
+ add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/true);
+ else if (is_sync_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool()))
+ add_defs(node, conn.second, /*fully_sync=*/true, /*elidable=*/false);
else if (is_internal_cell(cell->type))
- add_defs(node, conn.second, /*elidable=*/false);
- else {
- // Unlike outputs of internal cells (which generate code that depends on the ability to set the output
- // wire bits), outputs of user cells are normal wires, and the wires connected to them can be elided.
- add_defs(node, conn.second, /*elidable=*/true);
+ add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
+ else if (!is_cxxrtl_sync_port(cell, conn.first)) {
+ // Although at first it looks like outputs of user-defined cells may always be elided, the reality is
+ // more complex. Fully sync outputs produce no defs and so don't participate in elision. Fully comb
+ // outputs are assigned in a different way depending on whether the cell's eval() immediately converged.
+ // Unknown/mixed outputs could be elided, but should be rare in practical designs and don't justify
+ // the infrastructure required to elide outputs of cells with many of them.
+ add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false);
}
}
if (cell->input(conn.first))
@@ -307,11 +397,27 @@ struct FlowGraph {
Node *add_node(const RTLIL::Cell *cell)
{
+ log_assert(cell->known());
+
+ bool has_fully_sync_outputs = false;
+ for (auto conn : cell->connections())
+ if (cell->output(conn.first) && is_cxxrtl_sync_port(cell, conn.first)) {
+ has_fully_sync_outputs = true;
+ break;
+ }
+ if (has_fully_sync_outputs) {
+ Node *node = new Node;
+ node->type = Node::Type::CELL_SYNC;
+ node->cell = cell;
+ nodes.push_back(node);
+ add_cell_sync_defs(node, cell);
+ }
+
Node *node = new Node;
- node->type = Node::Type::CELL;
+ node->type = Node::Type::CELL_EVAL;
node->cell = cell;
nodes.push_back(node);
- add_cell_defs_uses(node, cell);
+ add_cell_eval_defs_uses(node, cell);
return node;
}
@@ -319,7 +425,7 @@ struct FlowGraph {
void add_case_defs_uses(Node *node, const RTLIL::CaseRule *case_)
{
for (auto &action : case_->actions) {
- add_defs(node, action.first, /*elidable=*/false);
+ add_defs(node, action.first, /*is_sync=*/false, /*elidable=*/false);
add_uses(node, action.second);
}
for (auto sub_switch : case_->switches) {
@@ -338,9 +444,9 @@ struct FlowGraph {
for (auto sync : process->syncs)
for (auto action : sync->actions) {
if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe)
- /* sync actions do not introduce feedback */;
+ add_defs(node, action.first, /*is_sync=*/true, /*elidable=*/false);
else
- add_defs(node, action.first, /*elidable=*/false);
+ add_defs(node, action.first, /*is_sync=*/false, /*elidable=*/false);
add_uses(node, action.second);
}
}
@@ -356,6 +462,46 @@ struct FlowGraph {
}
};
+std::vector<std::string> split_by(const std::string &str, const std::string &sep)
+{
+ std::vector<std::string> result;
+ size_t prev = 0;
+ while (true) {
+ size_t curr = str.find_first_of(sep, prev + 1);
+ if (curr > str.size())
+ curr = str.size();
+ if (curr > prev + 1)
+ result.push_back(str.substr(prev, curr - prev));
+ if (curr == str.size())
+ break;
+ prev = curr;
+ }
+ return result;
+}
+
+std::string escape_cxx_string(const std::string &input)
+{
+ std::string output = "\"";
+ for (auto c : input) {
+ if (::isprint(c)) {
+ if (c == '\\')
+ output.push_back('\\');
+ output.push_back(c);
+ } else {
+ char l = c & 0xf, h = (c >> 4) & 0xf;
+ output.append("\\x");
+ output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
+ output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
+ }
+ }
+ output.push_back('"');
+ if (output.find('\0') != std::string::npos) {
+ output.insert(0, "std::string {");
+ output.append(stringf(", %zu}", input.size()));
+ }
+ return output;
+}
+
struct CxxrtlWorker {
bool split_intf = false;
std::string intf_filename;
@@ -367,21 +513,24 @@ struct CxxrtlWorker {
bool elide_public = false;
bool localize_internal = false;
bool localize_public = false;
- bool run_splitnets = false;
+ bool run_opt_clean_purge = false;
+ bool run_proc_flatten = false;
+ bool max_opt_level = false;
std::ostringstream f;
std::string indent;
int temporary = 0;
dict<const RTLIL::Module*, SigMap> sigmaps;
- pool<const RTLIL::Wire*> sync_wires;
- dict<RTLIL::SigBit, RTLIL::SyncType> sync_types;
+ pool<const RTLIL::Wire*> edge_wires;
+ dict<RTLIL::SigBit, RTLIL::SyncType> edge_types;
pool<const RTLIL::Memory*> writable_memories;
dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for;
- dict<const RTLIL::Cell*, dict<RTLIL::Wire*, RTLIL::IdString>> cell_wire_defs;
dict<const RTLIL::Wire*, FlowGraph::Node> elided_wires;
dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule;
pool<const RTLIL::Wire*> localized_wires;
+ dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations;
+ dict<const RTLIL::Module*, bool> eval_converges;
void inc_indent() {
indent += "\t";
@@ -429,9 +578,11 @@ struct CxxrtlWorker {
return mangled;
}
- std::string mangle_module_name(const RTLIL::IdString &name)
+ std::string mangle_module_name(const RTLIL::IdString &name, bool is_blackbox = false)
{
// Class namespace.
+ if (is_blackbox)
+ return "bb_" + mangle_name(name);
return mangle_name(name);
}
@@ -455,7 +606,7 @@ struct CxxrtlWorker {
std::string mangle(const RTLIL::Module *module)
{
- return mangle_module_name(module->name);
+ return mangle_module_name(module->name, /*is_blackbox=*/module->get_bool_attribute(ID(cxxrtl.blackbox)));
}
std::string mangle(const RTLIL::Memory *memory)
@@ -481,6 +632,80 @@ struct CxxrtlWorker {
return mangle(sigbit.wire) + "_" + std::to_string(sigbit.offset);
}
+ std::vector<std::string> template_param_names(const RTLIL::Module *module)
+ {
+ if (!module->has_attribute(ID(cxxrtl.template)))
+ return {};
+
+ if (module->attributes.at(ID(cxxrtl.template)).flags != RTLIL::CONST_FLAG_STRING)
+ log_cmd_error("Attribute `cxxrtl.template' of module `%s' is not a string.\n", log_id(module));
+
+ std::vector<std::string> param_names = split_by(module->get_string_attribute(ID(cxxrtl.template)), " \t");
+ for (const auto &param_name : param_names) {
+ // Various lowercase prefixes (p_, i_, cell_, ...) are used for member variables, so require
+ // parameters to start with an uppercase letter to avoid name conflicts. (This is the convention
+ // in both Verilog and C++, anyway.)
+ if (!isupper(param_name[0]))
+ log_cmd_error("Attribute `cxxrtl.template' of module `%s' includes a parameter `%s', "
+ "which does not start with an uppercase letter.\n",
+ log_id(module), param_name.c_str());
+ }
+ return param_names;
+ }
+
+ std::string template_params(const RTLIL::Module *module, bool is_decl)
+ {
+ std::vector<std::string> param_names = template_param_names(module);
+ if (param_names.empty())
+ return "";
+
+ std::string params = "<";
+ bool first = true;
+ for (const auto &param_name : param_names) {
+ if (!first)
+ params += ", ";
+ first = false;
+ if (is_decl)
+ params += "size_t ";
+ params += param_name;
+ }
+ params += ">";
+ return params;
+ }
+
+ std::string template_args(const RTLIL::Cell *cell)
+ {
+ RTLIL::Module *cell_module = cell->module->design->module(cell->type);
+ log_assert(cell_module != nullptr);
+ if (!cell_module->get_bool_attribute(ID(cxxrtl.blackbox)))
+ return "";
+
+ std::vector<std::string> param_names = template_param_names(cell_module);
+ if (param_names.empty())
+ return "";
+
+ std::string params = "<";
+ bool first = true;
+ for (const auto &param_name : param_names) {
+ if (!first)
+ params += ", ";
+ first = false;
+ params += "/*" + param_name + "=*/";
+ RTLIL::IdString id_param_name = '\\' + param_name;
+ if (!cell->hasParam(id_param_name))
+ log_cmd_error("Cell `%s.%s' does not have a parameter `%s', which is required by the templated module `%s'.\n",
+ log_id(cell->module), log_id(cell), param_name.c_str(), log_id(cell_module));
+ RTLIL::Const param_value = cell->getParam(id_param_name);
+ if (((param_value.flags & ~RTLIL::CONST_FLAG_SIGNED) != 0) || param_value.as_int() < 0)
+ log_cmd_error("Parameter `%s' of cell `%s.%s', which is required by the templated module `%s', "
+ "is not a positive integer.\n",
+ param_name.c_str(), log_id(cell->module), log_id(cell), log_id(cell_module));
+ params += std::to_string(cell->getParam(id_param_name).as_int());
+ }
+ params += ">";
+ return params;
+ }
+
std::string fresh_temporary()
{
return stringf("tmp_%d", temporary++);
@@ -545,17 +770,14 @@ struct CxxrtlWorker {
case FlowGraph::Node::Type::CONNECT:
dump_connect_elided(node.connect);
break;
- case FlowGraph::Node::Type::CELL:
- if (is_elidable_cell(node.cell->type)) {
- dump_cell_elided(node.cell);
- } else {
- f << mangle(node.cell) << "." << mangle_wire_name(cell_wire_defs[node.cell][chunk.wire]) << ".curr";
- }
+ case FlowGraph::Node::Type::CELL_EVAL:
+ log_assert(is_elidable_cell(node.cell->type));
+ dump_cell_elided(node.cell);
break;
default:
log_assert(false);
}
- } else if (localized_wires[chunk.wire]) {
+ } else if (localized_wires[chunk.wire] || is_input_wire(chunk.wire)) {
f << mangle(chunk.wire);
} else {
f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
@@ -615,8 +837,8 @@ struct CxxrtlWorker {
case FlowGraph::Node::Type::CONNECT:
collect_connect(node.connect, cells);
break;
- case FlowGraph::Node::Type::CELL:
- collect_cell(node.cell, cells);
+ case FlowGraph::Node::Type::CELL_EVAL:
+ collect_cell_eval(node.cell, cells);
break;
default:
log_assert(false);
@@ -655,47 +877,60 @@ struct CxxrtlWorker {
f << ";\n";
}
+ void dump_cell_sync(const RTLIL::Cell *cell)
+ {
+ const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
+ f << indent << "// cell " << cell->name.str() << " syncs\n";
+ for (auto conn : cell->connections())
+ if (cell->output(conn.first))
+ if (is_cxxrtl_sync_port(cell, conn.first)) {
+ f << indent;
+ dump_sigspec_lhs(conn.second);
+ f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";
+ }
+ }
+
void dump_cell_elided(const RTLIL::Cell *cell)
{
// Unary cells
if (is_unary_cell(cell->type)) {
f << cell->type.substr(1) << '_' <<
- (cell->getParam(ID(A_SIGNED)).as_bool() ? 's' : 'u') <<
- "<" << cell->getParam(ID(Y_WIDTH)).as_int() << ">(";
- dump_sigspec_rhs(cell->getPort(ID(A)));
+ (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
+ "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
+ dump_sigspec_rhs(cell->getPort(ID::A));
f << ")";
// Binary cells
} else if (is_binary_cell(cell->type)) {
f << cell->type.substr(1) << '_' <<
- (cell->getParam(ID(A_SIGNED)).as_bool() ? 's' : 'u') <<
- (cell->getParam(ID(B_SIGNED)).as_bool() ? 's' : 'u') <<
- "<" << cell->getParam(ID(Y_WIDTH)).as_int() << ">(";
- dump_sigspec_rhs(cell->getPort(ID(A)));
+ (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
+ (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u') <<
+ "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
+ dump_sigspec_rhs(cell->getPort(ID::A));
f << ", ";
- dump_sigspec_rhs(cell->getPort(ID(B)));
+ dump_sigspec_rhs(cell->getPort(ID::B));
f << ")";
// Muxes
} else if (cell->type == ID($mux)) {
f << "(";
- dump_sigspec_rhs(cell->getPort(ID(S)));
+ dump_sigspec_rhs(cell->getPort(ID::S));
f << " ? ";
- dump_sigspec_rhs(cell->getPort(ID(B)));
+ dump_sigspec_rhs(cell->getPort(ID::B));
f << " : ";
- dump_sigspec_rhs(cell->getPort(ID(A)));
+ dump_sigspec_rhs(cell->getPort(ID::A));
f << ")";
// Concats
} else if (cell->type == ID($concat)) {
- dump_sigspec_rhs(cell->getPort(ID(B)));
+ dump_sigspec_rhs(cell->getPort(ID::B));
f << ".concat(";
- dump_sigspec_rhs(cell->getPort(ID(A)));
+ dump_sigspec_rhs(cell->getPort(ID::A));
f << ").val()";
// Slices
} else if (cell->type == ID($slice)) {
- dump_sigspec_rhs(cell->getPort(ID(A)));
+ dump_sigspec_rhs(cell->getPort(ID::A));
f << ".slice<";
- f << cell->getParam(ID(OFFSET)).as_int() + cell->getParam(ID(Y_WIDTH)).as_int() - 1;
+ f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
f << ",";
- f << cell->getParam(ID(OFFSET)).as_int();
+ f << cell->getParam(ID::OFFSET).as_int();
f << ">().val()";
} else {
log_assert(false);
@@ -704,22 +939,22 @@ struct CxxrtlWorker {
bool is_cell_elided(const RTLIL::Cell *cell)
{
- return is_elidable_cell(cell->type) && cell->hasPort(ID(Y)) && cell->getPort(ID(Y)).is_wire() &&
- elided_wires.count(cell->getPort(ID(Y)).as_wire());
+ return is_elidable_cell(cell->type) && cell->hasPort(ID::Y) && cell->getPort(ID::Y).is_wire() &&
+ elided_wires.count(cell->getPort(ID::Y).as_wire());
}
- void collect_cell(const RTLIL::Cell *cell, std::vector<RTLIL::IdString> &cells)
+ void collect_cell_eval(const RTLIL::Cell *cell, std::vector<RTLIL::IdString> &cells)
{
if (!is_cell_elided(cell))
return;
cells.push_back(cell->name);
for (auto port : cell->connections())
- if (port.first != ID(Y))
+ if (port.first != ID::Y)
collect_sigspec_rhs(port.second, cells);
}
- void dump_cell(const RTLIL::Cell *cell)
+ void dump_cell_eval(const RTLIL::Cell *cell)
{
if (is_cell_elided(cell))
return;
@@ -729,7 +964,7 @@ struct CxxrtlWorker {
std::vector<RTLIL::IdString> elided_cells;
if (is_elidable_cell(cell->type)) {
for (auto port : cell->connections())
- if (port.first != ID(Y))
+ if (port.first != ID::Y)
collect_sigspec_rhs(port.second, elided_cells);
}
if (elided_cells.empty()) {
@@ -745,26 +980,26 @@ struct CxxrtlWorker {
// Elidable cells
if (is_elidable_cell(cell->type)) {
f << indent;
- dump_sigspec_lhs(cell->getPort(ID(Y)));
+ dump_sigspec_lhs(cell->getPort(ID::Y));
f << " = ";
dump_cell_elided(cell);
f << ";\n";
// Parallel (one-hot) muxes
} else if (cell->type == ID($pmux)) {
- int width = cell->getParam(ID(WIDTH)).as_int();
- int s_width = cell->getParam(ID(S_WIDTH)).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int s_width = cell->getParam(ID::S_WIDTH).as_int();
bool first = true;
for (int part = 0; part < s_width; part++) {
f << (first ? indent : " else ");
first = false;
f << "if (";
- dump_sigspec_rhs(cell->getPort(ID(S)).extract(part));
+ dump_sigspec_rhs(cell->getPort(ID::S).extract(part));
f << ") {\n";
inc_indent();
f << indent;
- dump_sigspec_lhs(cell->getPort(ID(Y)));
+ dump_sigspec_lhs(cell->getPort(ID::Y));
f << " = ";
- dump_sigspec_rhs(cell->getPort(ID(B)).extract(part * width, width));
+ dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width));
f << ";\n";
dec_indent();
f << indent << "}";
@@ -772,31 +1007,31 @@ struct CxxrtlWorker {
f << " else {\n";
inc_indent();
f << indent;
- dump_sigspec_lhs(cell->getPort(ID(Y)));
+ dump_sigspec_lhs(cell->getPort(ID::Y));
f << " = ";
- dump_sigspec_rhs(cell->getPort(ID(A)));
+ dump_sigspec_rhs(cell->getPort(ID::A));
f << ";\n";
dec_indent();
f << indent << "}\n";
// Flip-flops
} else if (is_ff_cell(cell->type)) {
- if (cell->hasPort(ID(CLK)) && cell->getPort(ID(CLK)).is_wire()) {
+ if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) {
// Edge-sensitive logic
- RTLIL::SigBit clk_bit = cell->getPort(ID(CLK))[0];
+ RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
- f << indent << "if (" << (cell->getParam(ID(CLK_POLARITY)).as_bool() ? "posedge_" : "negedge_")
+ f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
<< mangle(clk_bit) << ") {\n";
inc_indent();
if (cell->type == ID($dffe)) {
f << indent << "if (";
- dump_sigspec_rhs(cell->getPort(ID(EN)));
- f << " == value<1> {" << cell->getParam(ID(EN_POLARITY)).as_bool() << "u}) {\n";
+ dump_sigspec_rhs(cell->getPort(ID::EN));
+ f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
inc_indent();
}
f << indent;
- dump_sigspec_lhs(cell->getPort(ID(Q)));
+ dump_sigspec_lhs(cell->getPort(ID::Q));
f << " = ";
- dump_sigspec_rhs(cell->getPort(ID(D)));
+ dump_sigspec_rhs(cell->getPort(ID::D));
f << ";\n";
if (cell->type == ID($dffe)) {
dec_indent();
@@ -804,77 +1039,77 @@ struct CxxrtlWorker {
}
dec_indent();
f << indent << "}\n";
- } else if (cell->hasPort(ID(EN))) {
+ } else if (cell->hasPort(ID::EN)) {
// Level-sensitive logic
f << indent << "if (";
- dump_sigspec_rhs(cell->getPort(ID(EN)));
- f << " == value<1> {" << cell->getParam(ID(EN_POLARITY)).as_bool() << "u}) {\n";
+ dump_sigspec_rhs(cell->getPort(ID::EN));
+ f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
inc_indent();
f << indent;
- dump_sigspec_lhs(cell->getPort(ID(Q)));
+ dump_sigspec_lhs(cell->getPort(ID::Q));
f << " = ";
- dump_sigspec_rhs(cell->getPort(ID(D)));
+ dump_sigspec_rhs(cell->getPort(ID::D));
f << ";\n";
dec_indent();
f << indent << "}\n";
}
- if (cell->hasPort(ID(ARST))) {
+ if (cell->hasPort(ID::ARST)) {
// Asynchronous reset (entire coarse cell at once)
f << indent << "if (";
- dump_sigspec_rhs(cell->getPort(ID(ARST)));
- f << " == value<1> {" << cell->getParam(ID(ARST_POLARITY)).as_bool() << "u}) {\n";
+ dump_sigspec_rhs(cell->getPort(ID::ARST));
+ f << " == value<1> {" << cell->getParam(ID::ARST_POLARITY).as_bool() << "u}) {\n";
inc_indent();
f << indent;
- dump_sigspec_lhs(cell->getPort(ID(Q)));
+ dump_sigspec_lhs(cell->getPort(ID::Q));
f << " = ";
- dump_const(cell->getParam(ID(ARST_VALUE)));
+ dump_const(cell->getParam(ID::ARST_VALUE));
f << ";\n";
dec_indent();
f << indent << "}\n";
}
- if (cell->hasPort(ID(SET))) {
+ if (cell->hasPort(ID::SET)) {
// Asynchronous set (for individual bits)
f << indent;
- dump_sigspec_lhs(cell->getPort(ID(Q)));
+ dump_sigspec_lhs(cell->getPort(ID::Q));
f << " = ";
- dump_sigspec_lhs(cell->getPort(ID(Q)));
+ dump_sigspec_lhs(cell->getPort(ID::Q));
f << ".update(";
- dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID(WIDTH)).as_int()));
+ dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int()));
f << ", ";
- dump_sigspec_rhs(cell->getPort(ID(SET)));
- f << (cell->getParam(ID(SET_POLARITY)).as_bool() ? "" : ".bit_not()") << ");\n";
+ dump_sigspec_rhs(cell->getPort(ID::SET));
+ f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
}
- if (cell->hasPort(ID(CLR))) {
+ if (cell->hasPort(ID::CLR)) {
// Asynchronous clear (for individual bits; priority over set)
f << indent;
- dump_sigspec_lhs(cell->getPort(ID(Q)));
+ dump_sigspec_lhs(cell->getPort(ID::Q));
f << " = ";
- dump_sigspec_lhs(cell->getPort(ID(Q)));
+ dump_sigspec_lhs(cell->getPort(ID::Q));
f << ".update(";
- dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID(WIDTH)).as_int()));
+ dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int()));
f << ", ";
- dump_sigspec_rhs(cell->getPort(ID(CLR)));
- f << (cell->getParam(ID(CLR_POLARITY)).as_bool() ? "" : ".bit_not()") << ");\n";
+ dump_sigspec_rhs(cell->getPort(ID::CLR));
+ f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
}
// Memory ports
} else if (cell->type.in(ID($memrd), ID($memwr))) {
- if (cell->getParam(ID(CLK_ENABLE)).as_bool()) {
- RTLIL::SigBit clk_bit = cell->getPort(ID(CLK))[0];
+ if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
+ RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
- f << indent << "if (" << (cell->getParam(ID(CLK_POLARITY)).as_bool() ? "posedge_" : "negedge_")
+ f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
<< mangle(clk_bit) << ") {\n";
inc_indent();
}
- RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID(MEMID)).decode_string()];
+ RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
std::string valid_index_temp = fresh_temporary();
f << indent << "auto " << valid_index_temp << " = memory_index(";
- dump_sigspec_rhs(cell->getPort(ID(ADDR)));
+ dump_sigspec_rhs(cell->getPort(ID::ADDR));
f << ", " << memory->start_offset << ", " << memory->size << ");\n";
if (cell->type == ID($memrd)) {
- bool has_enable = cell->getParam(ID(CLK_ENABLE)).as_bool() && !cell->getPort(ID(EN)).is_fully_ones();
+ bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();
if (has_enable) {
f << indent << "if (";
- dump_sigspec_rhs(cell->getPort(ID(EN)));
+ dump_sigspec_rhs(cell->getPort(ID::EN));
f << ") {\n";
inc_indent();
}
@@ -890,8 +1125,8 @@ struct CxxrtlWorker {
inc_indent();
if (writable_memories[memory]) {
std::string addr_temp = fresh_temporary();
- f << indent << "const value<" << cell->getPort(ID(ADDR)).size() << "> &" << addr_temp << " = ";
- dump_sigspec_rhs(cell->getPort(ID(ADDR)));
+ f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = ";
+ dump_sigspec_rhs(cell->getPort(ID::ADDR));
f << ";\n";
std::string lhs_temp = fresh_temporary();
f << indent << "value<" << memory->width << "> " << lhs_temp << " = "
@@ -899,35 +1134,35 @@ struct CxxrtlWorker {
std::vector<const RTLIL::Cell*> memwr_cells(transparent_for[cell].begin(), transparent_for[cell].end());
std::sort(memwr_cells.begin(), memwr_cells.end(),
[](const RTLIL::Cell *a, const RTLIL::Cell *b) {
- return a->getParam(ID(PRIORITY)).as_int() < b->getParam(ID(PRIORITY)).as_int();
+ return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int();
});
for (auto memwr_cell : memwr_cells) {
f << indent << "if (" << addr_temp << " == ";
- dump_sigspec_rhs(memwr_cell->getPort(ID(ADDR)));
+ dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR));
f << ") {\n";
inc_indent();
f << indent << lhs_temp << " = " << lhs_temp;
f << ".update(";
- dump_sigspec_rhs(memwr_cell->getPort(ID(DATA)));
+ dump_sigspec_rhs(memwr_cell->getPort(ID::DATA));
f << ", ";
- dump_sigspec_rhs(memwr_cell->getPort(ID(EN)));
+ dump_sigspec_rhs(memwr_cell->getPort(ID::EN));
f << ");\n";
dec_indent();
f << indent << "}\n";
}
f << indent;
- dump_sigspec_lhs(cell->getPort(ID(DATA)));
+ dump_sigspec_lhs(cell->getPort(ID::DATA));
f << " = " << lhs_temp << ";\n";
} else {
f << indent;
- dump_sigspec_lhs(cell->getPort(ID(DATA)));
+ dump_sigspec_lhs(cell->getPort(ID::DATA));
f << " = " << mangle(memory) << "[" << valid_index_temp << ".index];\n";
}
dec_indent();
f << indent << "} else {\n";
inc_indent();
f << indent;
- dump_sigspec_lhs(cell->getPort(ID(DATA)));
+ dump_sigspec_lhs(cell->getPort(ID::DATA));
f << " = value<" << memory->width << "> {};\n";
dec_indent();
f << indent << "}\n";
@@ -944,14 +1179,14 @@ struct CxxrtlWorker {
f << indent << "if (" << valid_index_temp << ".valid) {\n";
inc_indent();
f << indent << mangle(memory) << ".update(" << valid_index_temp << ".index, ";
- dump_sigspec_rhs(cell->getPort(ID(DATA)));
+ dump_sigspec_rhs(cell->getPort(ID::DATA));
f << ", ";
- dump_sigspec_rhs(cell->getPort(ID(EN)));
- f << ", " << cell->getParam(ID(PRIORITY)).as_int() << ");\n";
+ dump_sigspec_rhs(cell->getPort(ID::EN));
+ f << ", " << cell->getParam(ID::PRIORITY).as_int() << ");\n";
dec_indent();
f << indent << "}\n";
}
- if (cell->getParam(ID(CLK_ENABLE)).as_bool()) {
+ if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
dec_indent();
f << indent << "}\n";
}
@@ -961,27 +1196,71 @@ struct CxxrtlWorker {
// User cells
} else {
log_assert(cell->known());
+ const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
for (auto conn : cell->connections())
- if (cell->input(conn.first)) {
- f << indent << mangle(cell) << "." << mangle_wire_name(conn.first) << ".next = ";
+ if (cell->input(conn.first) && !cell->output(conn.first)) {
+ f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << " = ";
+ dump_sigspec_rhs(conn.second);
+ f << ";\n";
+ if (getenv("CXXRTL_VOID_MY_WARRANTY")) {
+ // Until we have proper clock tree detection, this really awful hack that opportunistically
+ // propagates prev_* values for clocks can be used to estimate how much faster a design could
+ // be if only one clock edge was simulated by replacing:
+ // top.p_clk = value<1>{0u}; top.step();
+ // top.p_clk = value<1>{1u}; top.step();
+ // with:
+ // top.prev_p_clk = value<1>{0u}; top.p_clk = value<1>{1u}; top.step();
+ // Don't rely on this; it will be removed without warning.
+ RTLIL::Module *cell_module = cell->module->design->module(cell->type);
+ if (cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire()) {
+ RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first);
+ if (edge_wires[conn.second.as_wire()] && edge_wires[cell_module_wire]) {
+ f << indent << mangle(cell) << access << "prev_" << mangle(cell_module_wire) << " = ";
+ f << "prev_" << mangle(conn.second.as_wire()) << ";\n";
+ }
+ }
+ }
+ } else if (cell->input(conn.first)) {
+ f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << ".next = ";
dump_sigspec_rhs(conn.second);
f << ";\n";
}
- f << indent << mangle(cell) << ".eval();\n";
- for (auto conn : cell->connections()) {
- if (conn.second.is_wire()) {
- RTLIL::Wire *wire = conn.second.as_wire();
- if (elided_wires.count(wire) && cell_wire_defs[cell].count(wire))
- continue;
- }
- if (cell->output(conn.first)) {
- if (conn.second.empty())
- continue; // ignore disconnected ports
- f << indent;
- dump_sigspec_lhs(conn.second);
- f << " = " << mangle(cell) << "." << mangle_wire_name(conn.first) << ".curr;\n";
+ auto assign_from_outputs = [&](bool cell_converged) {
+ for (auto conn : cell->connections()) {
+ if (cell->output(conn.first)) {
+ if (conn.second.empty())
+ continue; // ignore disconnected ports
+ if (is_cxxrtl_sync_port(cell, conn.first))
+ continue; // fully sync ports are handled in CELL_SYNC nodes
+ f << indent;
+ dump_sigspec_lhs(conn.second);
+ f << " = " << mangle(cell) << access << mangle_wire_name(conn.first);
+ // Similarly to how there is no purpose to buffering cell inputs, there is also no purpose to buffering
+ // combinatorial cell outputs in case the cell converges within one cycle. (To convince yourself that
+ // this optimization is valid, consider that, since the cell converged within one cycle, it would not
+ // have any buffered wires if they were not output ports. Imagine inlining the cell's eval() function,
+ // and consider the fate of the localized wires that used to be output ports.)
+ //
+ // Unlike cell inputs (which are never buffered), it is not possible to know apriori whether the cell
+ // (which may be late bound) will converge immediately. Because of this, the choice between using .curr
+ // (appropriate for buffered outputs) and .next (appropriate for unbuffered outputs) is made at runtime.
+ if (cell_converged && is_cxxrtl_comb_port(cell, conn.first))
+ f << ".next;\n";
+ else
+ f << ".curr;\n";
+ }
}
- }
+ };
+ f << indent << "if (" << mangle(cell) << access << "eval()) {\n";
+ inc_indent();
+ assign_from_outputs(/*cell_converged=*/true);
+ dec_indent();
+ f << indent << "} else {\n";
+ inc_indent();
+ f << indent << "converged = false;\n";
+ assign_from_outputs(/*cell_converged=*/false);
+ dec_indent();
+ f << indent << "}\n";
}
}
@@ -1076,24 +1355,34 @@ struct CxxrtlWorker {
log_assert(proc->root_case.attributes.empty());
dump_case_rule(&proc->root_case);
for (auto sync : proc->syncs) {
- RTLIL::SigBit sync_bit = sync->signal[0];
- sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
+ RTLIL::SigBit sync_bit;
+ if (!sync->signal.empty()) {
+ sync_bit = sync->signal[0];
+ sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
+ }
pool<std::string> events;
switch (sync->type) {
case RTLIL::STp:
+ log_assert(sync_bit.wire != nullptr);
events.insert("posedge_" + mangle(sync_bit));
break;
case RTLIL::STn:
+ log_assert(sync_bit.wire != nullptr);
events.insert("negedge_" + mangle(sync_bit));
+ break;
case RTLIL::STe:
+ log_assert(sync_bit.wire != nullptr);
events.insert("posedge_" + mangle(sync_bit));
events.insert("negedge_" + mangle(sync_bit));
break;
+ case RTLIL::STa:
+ events.insert("true");
+ break;
+
case RTLIL::ST0:
case RTLIL::ST1:
- case RTLIL::STa:
case RTLIL::STg:
case RTLIL::STi:
log_assert(false);
@@ -1117,35 +1406,66 @@ struct CxxrtlWorker {
}
}
- void dump_wire(const RTLIL::Wire *wire, bool is_local)
+ void dump_wire(const RTLIL::Wire *wire, bool is_local_context)
{
if (elided_wires.count(wire))
return;
+ if (localized_wires.count(wire) != is_local_context)
+ return;
- if (is_local) {
- if (!localized_wires.count(wire))
- return;
-
+ if (is_local_context) {
dump_attrs(wire);
f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
} else {
- if (localized_wires.count(wire))
- return;
+ std::string width;
+ if (wire->module->has_attribute(ID(cxxrtl.blackbox)) && wire->has_attribute(ID(cxxrtl.width))) {
+ width = wire->get_string_attribute(ID(cxxrtl.width));
+ } else {
+ width = std::to_string(wire->width);
+ }
dump_attrs(wire);
- f << indent << "wire<" << wire->width << "> " << mangle(wire);
- if (wire->attributes.count(ID(init))) {
+ f << indent << (is_input_wire(wire) ? "value" : "wire") << "<" << width << "> " << mangle(wire);
+ if (wire->has_attribute(ID::init)) {
f << " ";
- dump_const_init(wire->attributes.at(ID(init)));
+ dump_const_init(wire->attributes.at(ID::init));
}
f << ";\n";
- if (sync_wires[wire]) {
- for (auto sync_type : sync_types) {
- if (sync_type.first.wire == wire) {
- if (sync_type.second != RTLIL::STn)
- f << indent << "bool posedge_" << mangle(sync_type.first) << " = false;\n";
- if (sync_type.second != RTLIL::STp)
- f << indent << "bool negedge_" << mangle(sync_type.first) << " = false;\n";
+ if (edge_wires[wire]) {
+ if (is_input_wire(wire)) {
+ f << indent << "value<" << width << "> prev_" << mangle(wire);
+ if (wire->has_attribute(ID::init)) {
+ f << " ";
+ dump_const_init(wire->attributes.at(ID::init));
+ }
+ f << ";\n";
+ }
+ for (auto edge_type : edge_types) {
+ if (edge_type.first.wire == wire) {
+ std::string prev, next;
+ if (is_input_wire(wire)) {
+ prev = "prev_" + mangle(edge_type.first.wire);
+ next = mangle(edge_type.first.wire);
+ } else {
+ prev = mangle(edge_type.first.wire) + ".curr";
+ next = mangle(edge_type.first.wire) + ".next";
+ }
+ prev += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
+ next += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()";
+ if (edge_type.second != RTLIL::STn) {
+ f << indent << "bool posedge_" << mangle(edge_type.first) << "() const {\n";
+ inc_indent();
+ f << indent << "return !" << prev << " && " << next << ";\n";
+ dec_indent();
+ f << indent << "}\n";
+ }
+ if (edge_type.second != RTLIL::STp) {
+ f << indent << "bool negedge_" << mangle(edge_type.first) << "() const {\n";
+ inc_indent();
+ f << indent << "return " << prev << " && !" << next << ";\n";
+ dec_indent();
+ f << indent << "}\n";
+ }
}
}
}
@@ -1156,18 +1476,17 @@ struct CxxrtlWorker {
{
vector<const RTLIL::Cell*> init_cells;
for (auto cell : module->cells())
- if (cell->type == ID($meminit) && cell->getParam(ID(MEMID)).decode_string() == memory->name.str())
+ if (cell->type == ID($meminit) && cell->getParam(ID::MEMID).decode_string() == memory->name.str())
init_cells.push_back(cell);
std::sort(init_cells.begin(), init_cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
- int a_addr = a->getPort(ID(ADDR)).as_int(), b_addr = b->getPort(ID(ADDR)).as_int();
- int a_prio = a->getParam(ID(PRIORITY)).as_int(), b_prio = b->getParam(ID(PRIORITY)).as_int();
+ int a_addr = a->getPort(ID::ADDR).as_int(), b_addr = b->getPort(ID::ADDR).as_int();
+ int a_prio = a->getParam(ID::PRIORITY).as_int(), b_prio = b->getParam(ID::PRIORITY).as_int();
return a_prio > b_prio || (a_prio == b_prio && a_addr < b_addr);
});
dump_attrs(memory);
- f << indent << (writable_memories[memory] ? "" : "const ")
- << "memory<" << memory->width << "> " << mangle(memory)
+ f << indent << "memory<" << memory->width << "> " << mangle(memory)
<< " { " << memory->size << "u";
if (init_cells.empty()) {
f << " };\n";
@@ -1176,11 +1495,11 @@ struct CxxrtlWorker {
inc_indent();
for (auto cell : init_cells) {
dump_attrs(cell);
- RTLIL::Const data = cell->getPort(ID(DATA)).as_const();
- size_t width = cell->getParam(ID(WIDTH)).as_int();
- size_t words = cell->getParam(ID(WORDS)).as_int();
+ RTLIL::Const data = cell->getPort(ID::DATA).as_const();
+ size_t width = cell->getParam(ID::WIDTH).as_int();
+ size_t words = cell->getParam(ID::WORDS).as_int();
f << indent << "memory<" << memory->width << ">::init<" << words << "> { "
- << stringf("%#x", cell->getPort(ID(ADDR)).as_int()) << ", {";
+ << stringf("%#x", cell->getPort(ID::ADDR).as_int()) << ", {";
inc_indent();
for (size_t n = 0; n < words; n++) {
if (n % 4 == 0)
@@ -1198,140 +1517,235 @@ struct CxxrtlWorker {
}
}
- void dump_module_intf(RTLIL::Module *module)
+ void dump_eval_method(RTLIL::Module *module)
{
- dump_attrs(module);
- f << "struct " << mangle(module) << " : public module {\n";
inc_indent();
- for (auto wire : module->wires())
- dump_wire(wire, /*is_local=*/false);
- f << "\n";
- bool has_memories = false;
- for (auto memory : module->memories) {
- dump_memory(module, memory.second);
- has_memories = true;
- }
- if (has_memories)
- f << "\n";
- bool has_cells = false;
- for (auto cell : module->cells()) {
- if (is_internal_cell(cell->type))
- continue;
- f << indent << mangle_module_name(cell->type) << " " << mangle(cell) << ";\n";
- has_cells = true;
+ f << indent << "bool converged = " << (eval_converges.at(module) ? "true" : "false") << ";\n";
+ if (!module->get_bool_attribute(ID(cxxrtl.blackbox))) {
+ for (auto wire : module->wires()) {
+ if (edge_wires[wire]) {
+ for (auto edge_type : edge_types) {
+ if (edge_type.first.wire == wire) {
+ if (edge_type.second != RTLIL::STn) {
+ f << indent << "bool posedge_" << mangle(edge_type.first) << " = ";
+ f << "this->posedge_" << mangle(edge_type.first) << "();\n";
+ }
+ if (edge_type.second != RTLIL::STp) {
+ f << indent << "bool negedge_" << mangle(edge_type.first) << " = ";
+ f << "this->negedge_" << mangle(edge_type.first) << "();\n";
+ }
+ }
+ }
+ }
+ }
+ for (auto wire : module->wires())
+ dump_wire(wire, /*is_local_context=*/true);
+ for (auto node : schedule[module]) {
+ switch (node.type) {
+ case FlowGraph::Node::Type::CONNECT:
+ dump_connect(node.connect);
+ break;
+ case FlowGraph::Node::Type::CELL_SYNC:
+ dump_cell_sync(node.cell);
+ break;
+ case FlowGraph::Node::Type::CELL_EVAL:
+ dump_cell_eval(node.cell);
+ break;
+ case FlowGraph::Node::Type::PROCESS:
+ dump_process(node.process);
+ break;
+ }
+ }
}
- if (has_cells)
- f << "\n";
- f << indent << "void eval() override;\n";
- f << indent << "bool commit() override;\n";
+ f << indent << "return converged;\n";
dec_indent();
- f << "}; // struct " << mangle(module) << "\n";
- f << "\n";
}
- void dump_module_impl(RTLIL::Module *module)
+ void dump_commit_method(RTLIL::Module *module)
{
- f << "void " << mangle(module) << "::eval() {\n";
inc_indent();
- for (auto wire : module->wires())
- dump_wire(wire, /*is_local=*/true);
- for (auto node : schedule[module]) {
- switch (node.type) {
- case FlowGraph::Node::Type::CONNECT:
- dump_connect(node.connect);
- break;
- case FlowGraph::Node::Type::CELL:
- dump_cell(node.cell);
- break;
- case FlowGraph::Node::Type::PROCESS:
- dump_process(node.process);
- break;
+ f << indent << "bool changed = false;\n";
+ for (auto wire : module->wires()) {
+ if (elided_wires.count(wire) || localized_wires.count(wire))
+ continue;
+ if (is_input_wire(wire)) {
+ if (edge_wires[wire])
+ f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
+ continue;
}
+ if (!module->get_bool_attribute(ID(cxxrtl.blackbox)) || wire->port_id != 0)
+ f << indent << "changed |= " << mangle(wire) << ".commit();\n";
}
- for (auto sync_type : sync_types) {
- if (sync_type.first.wire->module == module) {
- if (sync_type.second != RTLIL::STn)
- f << indent << "posedge_" << mangle(sync_type.first) << " = false;\n";
- if (sync_type.second != RTLIL::STp)
- f << indent << "negedge_" << mangle(sync_type.first) << " = false;\n";
+ if (!module->get_bool_attribute(ID(cxxrtl.blackbox))) {
+ for (auto memory : module->memories) {
+ if (!writable_memories[memory.second])
+ continue;
+ f << indent << "changed |= " << mangle(memory.second) << ".commit();\n";
+ }
+ for (auto cell : module->cells()) {
+ if (is_internal_cell(cell->type))
+ continue;
+ const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
+ f << indent << "changed |= " << mangle(cell) << access << "commit();\n";
}
}
+ f << indent << "return changed;\n";
dec_indent();
- f << "}\n";
- f << "\n";
+ }
- f << "bool " << mangle(module) << "::commit() {\n";
+ void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
+ {
+ if (metadata_map.empty()) {
+ f << "metadata_map()";
+ return;
+ }
+ f << "metadata_map({\n";
inc_indent();
- f << indent << "bool changed = false;\n";
- for (auto wire : module->wires()) {
- if (elided_wires.count(wire) || localized_wires.count(wire))
+ for (auto metadata_item : metadata_map) {
+ if (!metadata_item.first.begins_with("\\"))
continue;
- if (sync_wires[wire]) {
- std::string wire_prev = mangle(wire) + "_prev";
- std::string wire_curr = mangle(wire) + ".curr";
- std::string wire_edge = mangle(wire) + "_edge";
- f << indent << "value<" << wire->width << "> " << wire_prev << " = " << wire_curr << ";\n";
- f << indent << "if (" << mangle(wire) << ".commit()) {\n";
- inc_indent();
- f << indent << "value<" << wire->width << "> " << wire_edge << " = "
- << wire_prev << ".bit_xor(" << wire_curr << ");\n";
- for (auto sync_type : sync_types) {
- if (sync_type.first.wire != wire)
- continue;
- if (sync_type.second != RTLIL::STn) {
- f << indent << "if (" << wire_edge << ".slice<" << sync_type.first.offset << ">().val() && "
- << wire_curr << ".slice<" << sync_type.first.offset << ">().val())\n";
- inc_indent();
- f << indent << "posedge_" << mangle(sync_type.first) << " = true;\n";
- dec_indent();
- }
- if (sync_type.second != RTLIL::STp) {
- f << indent << "if (" << wire_edge << ".slice<" << sync_type.first.offset << ">().val() && "
- << "!" << wire_curr << ".slice<" << sync_type.first.offset << ">().val())\n";
- inc_indent();
- f << indent << "negedge_" << mangle(sync_type.first) << " = true;\n";
- dec_indent();
- }
- f << indent << "changed = true;\n";
- }
- dec_indent();
- f << indent << "}\n";
+ f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
+ if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
+ f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
+ } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
+ f << escape_cxx_string(metadata_item.second.decode_string());
} else {
- f << indent << "changed |= " << mangle(wire) << ".commit();\n";
+ f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED);
+ if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED))
+ f << "u";
}
+ f << " },\n";
}
- for (auto memory : module->memories) {
- if (!writable_memories[memory.second])
- continue;
- f << indent << "changed |= " << mangle(memory.second) << ".commit();\n";
- }
- for (auto cell : module->cells()) {
- if (is_internal_cell(cell->type))
- continue;
- f << indent << "changed |= " << mangle(cell) << ".commit();\n";
- }
- f << indent << "return changed;\n";
dec_indent();
- f << "}\n";
+ f << indent << "})";
+ }
+
+ void dump_module_intf(RTLIL::Module *module)
+ {
+ dump_attrs(module);
+ if (module->get_bool_attribute(ID(cxxrtl.blackbox))) {
+ if (module->has_attribute(ID(cxxrtl.template)))
+ f << indent << "template" << template_params(module, /*is_decl=*/true) << "\n";
+ f << indent << "struct " << mangle(module) << " : public module {\n";
+ inc_indent();
+ for (auto wire : module->wires()) {
+ if (wire->port_id != 0)
+ dump_wire(wire, /*is_local_context=*/false);
+ }
+ f << "\n";
+ f << indent << "bool eval() override {\n";
+ dump_eval_method(module);
+ f << indent << "}\n";
+ f << "\n";
+ f << indent << "bool commit() override {\n";
+ dump_commit_method(module);
+ f << indent << "}\n";
+ f << "\n";
+ f << indent << "static std::unique_ptr<" << mangle(module);
+ f << template_params(module, /*is_decl=*/false) << "> ";
+ f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
+ dec_indent();
+ f << indent << "}; // struct " << mangle(module) << "\n";
+ f << "\n";
+ if (blackbox_specializations.count(module)) {
+ // If templated black boxes are used, the constructor of any module which includes the black box cell
+ // (which calls the declared but not defined in the generated code `create` function) may only be used
+ // if (a) the create function is defined in the same translation unit, or (b) the create function has
+ // a forward-declared explicit specialization.
+ //
+ // Option (b) makes it possible to have the generated code and the black box implementation in different
+ // translation units, which is convenient. Of course, its downside is that black boxes must predefine
+ // a specialization for every combination of parameters the generated code may use; but since the main
+ // purpose of templated black boxes is abstracting over datapath width, it is expected that there would
+ // be very few such combinations anyway.
+ for (auto specialization : blackbox_specializations[module]) {
+ f << indent << "template<>\n";
+ f << indent << "std::unique_ptr<" << mangle(module) << specialization << "> ";
+ f << mangle(module) << specialization << "::";
+ f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
+ f << "\n";
+ }
+ }
+ } else {
+ f << indent << "struct " << mangle(module) << " : public module {\n";
+ inc_indent();
+ for (auto wire : module->wires())
+ dump_wire(wire, /*is_local_context=*/false);
+ f << "\n";
+ bool has_memories = false;
+ for (auto memory : module->memories) {
+ dump_memory(module, memory.second);
+ has_memories = true;
+ }
+ if (has_memories)
+ f << "\n";
+ bool has_cells = false;
+ for (auto cell : module->cells()) {
+ if (is_internal_cell(cell->type))
+ continue;
+ dump_attrs(cell);
+ RTLIL::Module *cell_module = module->design->module(cell->type);
+ log_assert(cell_module != nullptr);
+ if (cell_module->get_bool_attribute(ID(cxxrtl.blackbox))) {
+ f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
+ f << mangle(cell) << " = " << mangle(cell_module) << template_args(cell);
+ f << "::create(" << escape_cxx_string(cell->name.str()) << ", ";
+ dump_metadata_map(cell->parameters);
+ f << ", ";
+ dump_metadata_map(cell->attributes);
+ f << ");\n";
+ } else {
+ f << indent << mangle(cell_module) << " " << mangle(cell) << ";\n";
+ }
+ has_cells = true;
+ }
+ if (has_cells)
+ f << "\n";
+ f << indent << "bool eval() override;\n";
+ f << indent << "bool commit() override;\n";
+ dec_indent();
+ f << indent << "}; // struct " << mangle(module) << "\n";
+ f << "\n";
+ }
+ }
+
+ void dump_module_impl(RTLIL::Module *module)
+ {
+ if (module->get_bool_attribute(ID(cxxrtl.blackbox)))
+ return;
+ f << indent << "bool " << mangle(module) << "::eval() {\n";
+ dump_eval_method(module);
+ f << indent << "}\n";
+ f << "\n";
+ f << indent << "bool " << mangle(module) << "::commit() {\n";
+ dump_commit_method(module);
+ f << indent << "}\n";
f << "\n";
}
void dump_design(RTLIL::Design *design)
{
+ std::vector<RTLIL::Module*> modules;
TopoSort<RTLIL::Module*> topo_design;
for (auto module : design->modules()) {
- if (module->get_blackbox_attribute() || !design->selected_module(module))
+ if (!design->selected_module(module))
+ continue;
+ if (module->get_bool_attribute(ID(cxxrtl.blackbox)))
+ modules.push_back(module); // cxxrtl blackboxes first
+ if (module->get_blackbox_attribute() || module->get_bool_attribute(ID(cxxrtl.blackbox)))
continue;
- topo_design.node(module);
+ topo_design.node(module);
for (auto cell : module->cells()) {
- if (is_internal_cell(cell->type))
+ if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
continue;
- log_assert(design->has(cell->type));
- topo_design.edge(design->module(cell->type), module);
+ RTLIL::Module *cell_module = design->module(cell->type);
+ log_assert(cell_module != nullptr);
+ topo_design.edge(cell_module, module);
}
}
log_assert(topo_design.sort());
+ modules.insert(modules.end(), topo_design.sorted.begin(), topo_design.sorted.end());
if (split_intf) {
// The only thing more depraved than include guards, is mangling filenames to turn them into include guards.
@@ -1347,11 +1761,8 @@ struct CxxrtlWorker {
f << "\n";
f << "namespace " << design_ns << " {\n";
f << "\n";
- for (auto module : topo_design.sorted) {
- if (!design->selected_module(module))
- continue;
+ for (auto module : modules)
dump_module_intf(module);
- }
f << "} // namespace " << design_ns << "\n";
f << "\n";
f << "#endif\n";
@@ -1367,9 +1778,7 @@ struct CxxrtlWorker {
f << "\n";
f << "namespace " << design_ns << " {\n";
f << "\n";
- for (auto module : topo_design.sorted) {
- if (!design->selected_module(module))
- continue;
+ for (auto module : modules) {
if (!split_intf)
dump_module_intf(module);
dump_module_impl(module);
@@ -1393,24 +1802,59 @@ struct CxxrtlWorker {
log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe);
RTLIL::SigBit sigbit = signal[0];
- if (!sync_types.count(sigbit))
- sync_types[sigbit] = type;
- else if (sync_types[sigbit] != type)
- sync_types[sigbit] = RTLIL::STe;
- sync_wires.insert(signal.as_wire());
+ if (!edge_types.count(sigbit))
+ edge_types[sigbit] = type;
+ else if (edge_types[sigbit] != type)
+ edge_types[sigbit] = RTLIL::STe;
+ edge_wires.insert(signal.as_wire());
}
void analyze_design(RTLIL::Design *design)
{
bool has_feedback_arcs = false;
+ bool has_buffered_wires = false;
+
for (auto module : design->modules()) {
if (!design->selected_module(module))
continue;
- FlowGraph flow;
SigMap &sigmap = sigmaps[module];
sigmap.set(module);
+ if (module->get_bool_attribute(ID(cxxrtl.blackbox))) {
+ for (auto port : module->ports) {
+ RTLIL::Wire *wire = module->wire(port);
+ if (wire->has_attribute(ID(cxxrtl.edge))) {
+ RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl.edge)];
+ if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire))
+ log_cmd_error("Attribute `cxxrtl.edge' of port `%s.%s' is not a string with one character per bit.\n",
+ log_id(module), log_signal(wire));
+
+ std::string edges = wire->get_string_attribute(ID(cxxrtl.edge));
+ for (int i = 0; i < GetSize(wire); i++) {
+ RTLIL::SigSpec wire_sig = wire;
+ switch (edges[i]) {
+ case '-': break;
+ case 'p': register_edge_signal(sigmap, wire_sig[i], RTLIL::STp); break;
+ case 'n': register_edge_signal(sigmap, wire_sig[i], RTLIL::STn); break;
+ case 'a': register_edge_signal(sigmap, wire_sig[i], RTLIL::STe); break;
+ default:
+ log_cmd_error("Attribute `cxxrtl.edge' of port `%s.%s' contains specifiers "
+ "other than '-', 'p', 'n', or 'a'.\n",
+ log_id(module), log_signal(wire));
+ }
+ }
+ }
+ }
+
+ // Black boxes converge by default, since their implementations are quite unlikely to require
+ // internal propagation of comb signals.
+ eval_converges[module] = true;
+ continue;
+ }
+
+ FlowGraph flow;
+
for (auto conn : module->connections())
flow.add_node(conn);
@@ -1418,32 +1862,44 @@ struct CxxrtlWorker {
dict<std::pair<RTLIL::SigBit, const RTLIL::Memory*>,
pool<const RTLIL::Cell*>> memwr_per_domain;
for (auto cell : module->cells()) {
+ if (!cell->known())
+ log_cmd_error("Unknown cell `%s'.\n", log_id(cell->type));
+
+ RTLIL::Module *cell_module = design->module(cell->type);
+ if (cell_module &&
+ cell_module->get_blackbox_attribute() &&
+ !cell_module->get_bool_attribute(ID(cxxrtl.blackbox)))
+ log_cmd_error("External blackbox cell `%s' is not marked as a CXXRTL blackbox.\n", log_id(cell->type));
+
+ if (cell_module &&
+ cell_module->get_bool_attribute(ID(cxxrtl.blackbox)) &&
+ cell_module->get_bool_attribute(ID(cxxrtl.template)))
+ blackbox_specializations[cell_module].insert(template_args(cell));
+
FlowGraph::Node *node = flow.add_node(cell);
// Various DFF cells are treated like posedge/negedge processes, see above for details.
if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($dffsr))) {
- if (cell->getPort(ID(CLK)).is_wire())
- register_edge_signal(sigmap, cell->getPort(ID(CLK)),
- cell->parameters[ID(CLK_POLARITY)].as_bool() ? RTLIL::STp : RTLIL::STn);
- // The $adff and $dffsr cells are level-sensitive, not edge-sensitive (in spite of the fact that they
- // are inferred from an edge-sensitive Verilog process) and do not correspond to an edge-type sync rule.
+ if (cell->getPort(ID::CLK).is_wire())
+ register_edge_signal(sigmap, cell->getPort(ID::CLK),
+ cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
}
// Similar for memory port cells.
if (cell->type.in(ID($memrd), ID($memwr))) {
- if (cell->getParam(ID(CLK_ENABLE)).as_bool()) {
- if (cell->getPort(ID(CLK)).is_wire())
- register_edge_signal(sigmap, cell->getPort(ID(CLK)),
- cell->parameters[ID(CLK_POLARITY)].as_bool() ? RTLIL::STp : RTLIL::STn);
+ if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
+ if (cell->getPort(ID::CLK).is_wire())
+ register_edge_signal(sigmap, cell->getPort(ID::CLK),
+ cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
}
memrw_cell_nodes[cell] = node;
}
// Optimize access to read-only memories.
if (cell->type == ID($memwr))
- writable_memories.insert(module->memories[cell->getParam(ID(MEMID)).decode_string()]);
+ writable_memories.insert(module->memories[cell->getParam(ID::MEMID).decode_string()]);
// Collect groups of memory write ports in the same domain.
- if (cell->type == ID($memwr) && cell->getParam(ID(CLK_ENABLE)).as_bool() && cell->getPort(ID(CLK)).is_wire()) {
- RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID(CLK)))[0];
- const RTLIL::Memory *memory = module->memories[cell->getParam(ID(MEMID)).decode_string()];
+ if (cell->type == ID($memwr) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire()) {
+ RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
+ const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
memwr_per_domain[{clk_bit, memory}].insert(cell);
}
// Handling of packed memories is delegated to the `memory_unpack` pass, so we can rely on the presence
@@ -1453,17 +1909,17 @@ struct CxxrtlWorker {
}
for (auto cell : module->cells()) {
// Collect groups of memory write ports read by every transparent read port.
- if (cell->type == ID($memrd) && cell->getParam(ID(CLK_ENABLE)).as_bool() && cell->getPort(ID(CLK)).is_wire() &&
- cell->getParam(ID(TRANSPARENT)).as_bool()) {
- RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID(CLK)))[0];
- const RTLIL::Memory *memory = module->memories[cell->getParam(ID(MEMID)).decode_string()];
+ if (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire() &&
+ cell->getParam(ID::TRANSPARENT).as_bool()) {
+ RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0];
+ const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()];
for (auto memwr_cell : memwr_per_domain[{clk_bit, memory}]) {
transparent_for[cell].insert(memwr_cell);
// Our implementation of transparent $memrd cells reads \EN, \ADDR and \DATA from every $memwr cell
// in the same domain, which isn't directly visible in the netlist. Add these uses explicitly.
- flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID(EN)));
- flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID(ADDR)));
- flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID(DATA)));
+ flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::EN));
+ flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::ADDR));
+ flow.add_uses(memrw_cell_nodes[cell], memwr_cell->getPort(ID::DATA));
}
}
}
@@ -1499,26 +1955,18 @@ struct CxxrtlWorker {
for (auto wire : module->wires()) {
if (!flow.is_elidable(wire)) continue;
if (wire->port_id != 0) continue;
- if (wire->get_bool_attribute(ID(keep))) continue;
+ if (wire->get_bool_attribute(ID::keep)) continue;
if (wire->name.begins_with("$") && !elide_internal) continue;
if (wire->name.begins_with("\\") && !elide_public) continue;
- if (sync_wires[wire]) continue;
- log_assert(flow.wire_defs[wire].size() == 1);
- elided_wires[wire] = **flow.wire_defs[wire].begin();
+ if (edge_wires[wire]) continue;
+ log_assert(flow.wire_comb_defs[wire].size() == 1);
+ elided_wires[wire] = **flow.wire_comb_defs[wire].begin();
}
- // Elided wires that are outputs of internal cells are always connected to a well known port (Y).
- // For user cells, there could be multiple of them, and we need a way to look up the port name
- // knowing only the wire.
- for (auto cell : module->cells())
- for (auto conn : cell->connections())
- if (conn.second.is_wire() && elided_wires.count(conn.second.as_wire()))
- cell_wire_defs[cell][conn.second.as_wire()] = conn.first;
-
dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_defs;
- for (auto wire_def : flow.wire_defs)
- for (auto node : wire_def.second)
- node_defs[node].insert(wire_def.first);
+ for (auto wire_comb_def : flow.wire_comb_defs)
+ for (auto node : wire_comb_def.second)
+ node_defs[node].insert(wire_comb_def.first);
Scheduler<FlowGraph::Node> scheduler;
dict<FlowGraph::Node*, Scheduler<FlowGraph::Node>::Vertex*, hash_ptr_ops> node_map;
@@ -1557,26 +2005,57 @@ struct CxxrtlWorker {
if (!feedback_wires.empty()) {
has_feedback_arcs = true;
- log("Module `%s` contains feedback arcs through wires:\n", module->name.c_str());
- for (auto wire : feedback_wires) {
- log(" %s\n", wire->name.c_str());
- }
+ log("Module `%s' contains feedback arcs through wires:\n", log_id(module));
+ for (auto wire : feedback_wires)
+ log(" %s\n", log_id(wire));
}
for (auto wire : module->wires()) {
if (feedback_wires[wire]) continue;
if (wire->port_id != 0) continue;
- if (wire->get_bool_attribute(ID(keep))) continue;
+ if (wire->get_bool_attribute(ID::keep)) continue;
if (wire->name.begins_with("$") && !localize_internal) continue;
if (wire->name.begins_with("\\") && !localize_public) continue;
- if (sync_wires[wire]) continue;
- // Outputs of FF/$memrd cells and LHS of sync actions do not end up in defs.
- if (flow.wire_defs[wire].size() != 1) continue;
+ if (edge_wires[wire]) continue;
+ if (flow.wire_sync_defs.count(wire) > 0) continue;
localized_wires.insert(wire);
}
+
+ // For maximum performance, the state of the simulation (which is the same as the set of its double buffered
+ // wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain
+ // no wires attached to combinatorial outputs. Feedback wires, by definition, make that impossible. However,
+ // it is possible that a design with no feedback arcs would end up with doubly buffered wires in such cases
+ // as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs
+ // also require more than one delta cycle to converge.
+ pool<const RTLIL::Wire*> buffered_wires;
+ for (auto wire : module->wires()) {
+ if (flow.wire_comb_defs[wire].size() > 0 && !elided_wires.count(wire) && !localized_wires[wire]) {
+ if (!feedback_wires[wire])
+ buffered_wires.insert(wire);
+ }
+ }
+ if (!buffered_wires.empty()) {
+ has_buffered_wires = true;
+ log("Module `%s' contains buffered combinatorial wires:\n", log_id(module));
+ for (auto wire : buffered_wires)
+ log(" %s\n", log_id(wire));
+ }
+
+ eval_converges[module] = feedback_wires.empty() && buffered_wires.empty();
}
- if (has_feedback_arcs) {
- log("Feedback arcs require delta cycles during evaluation.\n");
+ if (has_feedback_arcs || has_buffered_wires) {
+ // Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
+ // by optimizing the design, if after `opt_clean -purge` there are any feedback wires remaining, it is very
+ // likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
+ const char *why_pessimistic = nullptr;
+ if (has_feedback_arcs)
+ why_pessimistic = "feedback wires";
+ else if (has_buffered_wires)
+ why_pessimistic = "buffered combinatorial wires";
+ log("\n");
+ log_warning("Design contains %s, which require delta cycles during evaluation.\n", why_pessimistic);
+ if (!max_opt_level)
+ log("Increasing the optimization level may eliminate %s from the design.\n", why_pessimistic);
}
}
@@ -1585,12 +2064,12 @@ struct CxxrtlWorker {
has_sync_init = has_packed_mem = false;
for (auto module : design->modules()) {
- if (module->get_blackbox_attribute())
+ if (module->get_blackbox_attribute() && !module->has_attribute(ID(cxxrtl.blackbox)))
continue;
if (!design->selected_whole_module(module))
if (design->selected_module(module))
- log_cmd_error("Can't handle partially selected module `%s`!\n", id2cstr(module->name));
+ log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name));
if (!design->selected_module(module))
continue;
@@ -1608,8 +2087,12 @@ struct CxxrtlWorker {
void prepare_design(RTLIL::Design *design)
{
bool has_sync_init, has_packed_mem;
+ log_push();
check_design(design, has_sync_init, has_packed_mem);
- if (has_sync_init) {
+ if (run_proc_flatten) {
+ Pass::call(design, "proc");
+ Pass::call(design, "flatten");
+ } else if (has_sync_init) {
// We're only interested in proc_init, but it depends on proc_prune and proc_clean, so call those
// in case they weren't already. (This allows `yosys foo.v -o foo.cc` to work.)
Pass::call(design, "proc_prune");
@@ -1622,18 +2105,15 @@ struct CxxrtlWorker {
if (has_sync_init || has_packed_mem)
check_design(design, has_sync_init, has_packed_mem);
log_assert(!(has_sync_init || has_packed_mem));
-
- if (run_splitnets) {
- Pass::call(design, "splitnets -driver");
+ if (run_opt_clean_purge)
Pass::call(design, "opt_clean -purge");
- }
- log("\n");
+ log_pop();
analyze_design(design);
}
};
struct CxxrtlBackend : public Backend {
- static const int DEFAULT_OPT_LEVEL = 5;
+ static const int DEFAULT_OPT_LEVEL = 6;
CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
void help() YS_OVERRIDE
@@ -1642,21 +2122,156 @@ struct CxxrtlBackend : public Backend {
log("\n");
log(" write_cxxrtl [options] [filename]\n");
log("\n");
- log("Write C++ code for simulating the design. The generated code requires a driver;\n");
- log("the following simple driver is provided as an example:\n");
+ log("Write C++ code that simulates the design. The generated code requires a driver\n");
+ log("that instantiates the design, toggles its clock, and interacts with its ports.\n");
+ log("\n");
+ log("The following driver may be used as an example for a design with a single clock\n");
+ log("driving rising edge triggered flip-flops:\n");
log("\n");
log(" #include \"top.cc\"\n");
log("\n");
log(" int main() {\n");
log(" cxxrtl_design::p_top top;\n");
+ log(" top.step();\n");
log(" while (1) {\n");
- log(" top.p_clk.next = value<1> {1u};\n");
+ log(" /* user logic */\n");
+ log(" top.p_clk = value<1> {0u};\n");
log(" top.step();\n");
- log(" top.p_clk.next = value<1> {0u};\n");
+ log(" top.p_clk = value<1> {1u};\n");
log(" top.step();\n");
log(" }\n");
log(" }\n");
log("\n");
+ log("Note that CXXRTL simulations, just like the hardware they are simulating, are\n");
+ log("subject to race conditions. If, in the example above, the user logic would run\n");
+ log("simultaneously with the rising edge of the clock, the design would malfunction.\n");
+ log("\n");
+ log("This backend supports replacing parts of the design with black boxes implemented\n");
+ log("in C++. If a module marked as a CXXRTL black box, its implementation is ignored,\n");
+ log("and the generated code consists only of an interface and a factory function.\n");
+ log("The driver must implement the factory function that creates an implementation of\n");
+ log("the black box, taking into account the parameters it is instantiated with.\n");
+ log("\n");
+ log("For example, the following Verilog code defines a CXXRTL black box interface for\n");
+ log("a synchronous debug sink:\n");
+ log("\n");
+ log(" (* cxxrtl.blackbox *)\n");
+ log(" module debug(...);\n");
+ log(" (* cxxrtl.edge = \"p\" *) input clk;\n");
+ log(" input en;\n");
+ log(" input [7:0] i_data;\n");
+ log(" (* cxxrtl.sync *) output [7:0] o_data;\n");
+ log(" endmodule\n");
+ log("\n");
+ log("For this HDL interface, this backend will generate the following C++ interface:\n");
+ log("\n");
+ log(" struct bb_p_debug : public module {\n");
+ log(" value<1> p_clk;\n");
+ log(" bool posedge_p_clk() const { /* ... */ }\n");
+ log(" value<1> p_en;\n");
+ log(" value<8> p_i_data;\n");
+ log(" wire<8> p_o_data;\n");
+ log("\n");
+ log(" bool eval() override;\n");
+ log(" bool commit() override;\n");
+ log("\n");
+ log(" static std::unique_ptr<bb_p_debug>\n");
+ log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
+ log(" };\n");
+ log("\n");
+ log("The `create' function must be implemented by the driver. For example, it could\n");
+ log("always provide an implementation logging the values to standard error stream:\n");
+ log("\n");
+ log(" namespace cxxrtl_design {\n");
+ log("\n");
+ log(" struct stderr_debug : public bb_p_debug {\n");
+ log(" bool eval() override {\n");
+ log(" if (posedge_p_clk() && p_en)\n");
+ log(" fprintf(stderr, \"debug: %%02x\\n\", p_i_data.data[0]);\n");
+ log(" p_o_data.next = p_i_data;\n");
+ log(" return bb_p_debug::eval();\n");
+ log(" }\n");
+ log(" };\n");
+ log("\n");
+ log(" std::unique_ptr<bb_p_debug>\n");
+ log(" bb_p_debug::create(std::string name, cxxrtl::metadata_map parameters,\n");
+ log(" cxxrtl::metadata_map attributes) {\n");
+ log(" return std::make_unique<stderr_debug>();\n");
+ log(" }\n");
+ log("\n");
+ log(" }\n");
+ log("\n");
+ log("For complex applications of black boxes, it is possible to parameterize their\n");
+ log("port widths. For example, the following Verilog code defines a CXXRTL black box\n");
+ log("interface for a configurable width debug sink:\n");
+ log("\n");
+ log(" (* cxxrtl.blackbox, cxxrtl.template = \"WIDTH\" *)\n");
+ log(" module debug(...);\n");
+ log(" parameter WIDTH = 8;\n");
+ log(" (* cxxrtl.edge = \"p\" *) input clk;\n");
+ log(" input en;\n");
+ log(" (* cxxrtl.width = \"WIDTH\" *) input [WIDTH - 1:0] i_data;\n");
+ log(" (* cxxrtl.width = \"WIDTH\" *) output [WIDTH - 1:0] o_data;\n");
+ log(" endmodule\n");
+ log("\n");
+ log("For this parametric HDL interface, this backend will generate the following C++\n");
+ log("interface (only the differences are shown):\n");
+ log("\n");
+ log(" template<size_t WIDTH>\n");
+ log(" struct bb_p_debug : public module {\n");
+ log(" // ...\n");
+ log(" value<WIDTH> p_i_data;\n");
+ log(" wire<WIDTH> p_o_data;\n");
+ log(" // ...\n");
+ log(" static std::unique_ptr<bb_p_debug<WIDTH>>\n");
+ log(" create(std::string name, metadata_map parameters, metadata_map attributes);\n");
+ log(" };\n");
+ log("\n");
+ log("The `create' function must be implemented by the driver, specialized for every\n");
+ log("possible combination of template parameters. (Specialization is necessary to\n");
+ log("enable separate compilation of generated code and black box implementations.)\n");
+ log("\n");
+ log(" template<size_t SIZE>\n");
+ log(" struct stderr_debug : public bb_p_debug<SIZE> {\n");
+ log(" // ...\n");
+ log(" };\n");
+ log("\n");
+ log(" template<>\n");
+ log(" std::unique_ptr<bb_p_debug<8>>\n");
+ log(" bb_p_debug<8>::create(std::string name, cxxrtl::metadata_map parameters,\n");
+ log(" cxxrtl::metadata_map attributes) {\n");
+ log(" return std::make_unique<stderr_debug<8>>();\n");
+ log(" }\n");
+ log("\n");
+ log("The following attributes are recognized by this backend:\n");
+ log("\n");
+ log(" cxxrtl.blackbox\n");
+ log(" only valid on modules. if specified, the module contents are ignored,\n");
+ log(" and the generated code includes only the module interface and a factory\n");
+ log(" function, which will be called to instantiate the module.\n");
+ log("\n");
+ log(" cxxrtl.edge\n");
+ log(" only valid on inputs of black boxes. must be one of \"p\", \"n\", \"a\".\n");
+ log(" if specified on signal `clk`, the generated code includes edge detectors\n");
+ log(" `posedge_p_clk()` (if \"p\"), `negedge_p_clk()` (if \"n\"), or both (if\n");
+ log(" \"a\"), simplifying implementation of clocked black boxes.\n");
+ log("\n");
+ log(" cxxrtl.template\n");
+ log(" only valid on black boxes. must contain a space separated sequence of\n");
+ log(" identifiers that have a corresponding black box parameters. for each\n");
+ log(" of them, the generated code includes a `size_t` template parameter.\n");
+ log("\n");
+ log(" cxxrtl.width\n");
+ log(" only valid on ports of black boxes. must be a constant expression, which\n");
+ log(" is directly inserted into generated code.\n");
+ log("\n");
+ log(" cxxrtl.comb, cxxrtl.sync\n");
+ log(" only valid on outputs of black boxes. if specified, indicates that every\n");
+ log(" bit of the output port is driven, correspondingly, by combinatorial or\n");
+ log(" synchronous logic. this knowledge is used for scheduling optimizations.\n");
+ log(" if neither is specified, the output will be pessimistically treated as\n");
+ log(" driven by both combinatorial and synchronous logic.\n");
+ log("\n");
log("The following options are supported by this backend:\n");
log("\n");
log(" -header\n");
@@ -1690,7 +2305,10 @@ struct CxxrtlBackend : public Backend {
log(" like -O3, and localize public wires not marked (*keep*) if possible.\n");
log("\n");
log(" -O5\n");
- log(" like -O4, and run `splitnets -driver; opt_clean -purge` first.\n");
+ log(" like -O4, and run `opt_clean -purge` first.\n");
+ log("\n");
+ log(" -O6\n");
+ log(" like -O5, and run `proc; flatten` first.\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -1724,8 +2342,11 @@ struct CxxrtlBackend : public Backend {
extra_args(f, filename, args, argidx);
switch (opt_level) {
+ case 6:
+ worker.max_opt_level = true;
+ worker.run_proc_flatten = true;
case 5:
- worker.run_splitnets = true;
+ worker.run_opt_clean_purge = true;
case 4:
worker.localize_public = true;
case 3:
diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h
index 593c31c28..b79bbbc72 100644
--- a/backends/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/cxxrtl.h
@@ -28,7 +28,9 @@
#include <type_traits>
#include <tuple>
#include <vector>
+#include <map>
#include <algorithm>
+#include <memory>
#include <sstream>
// The cxxrtl support library implements compile time specialized arbitrary width arithmetics, as well as provides
@@ -604,12 +606,15 @@ struct memory {
auto _ = {std::move(std::begin(init.data), std::end(init.data), data.begin() + init.offset)...};
}
- value<Width> &operator [](size_t index) {
+ // An operator for direct memory reads. May be used at any time during the simulation.
+ const value<Width> &operator [](size_t index) const {
assert(index < data.size());
return data[index];
}
- const value<Width> &operator [](size_t index) const {
+ // An operator for direct memory writes. May only be used before the simulation is started. If used
+ // after the simulation is started, the design may malfunction.
+ value<Width> &operator [](size_t index) {
assert(index < data.size());
return data[index];
}
@@ -654,6 +659,57 @@ struct memory {
}
};
+struct metadata {
+ const enum {
+ MISSING = 0,
+ UINT = 1,
+ SINT = 2,
+ STRING = 3,
+ DOUBLE = 4,
+ } value_type;
+
+ // In debug mode, using the wrong .as_*() function will assert.
+ // In release mode, using the wrong .as_*() function will safely return a default value.
+ union {
+ const unsigned uint_value = 0;
+ const signed sint_value;
+ };
+ const std::string string_value = "";
+ const double double_value = 0.0;
+
+ metadata() : value_type(MISSING) {}
+ metadata(unsigned value) : value_type(UINT), uint_value(value) {}
+ metadata(signed value) : value_type(SINT), sint_value(value) {}
+ metadata(const std::string &value) : value_type(STRING), string_value(value) {}
+ metadata(const char *value) : value_type(STRING), string_value(value) {}
+ metadata(double value) : value_type(DOUBLE), double_value(value) {}
+
+ metadata(const metadata &) = default;
+ metadata &operator=(const metadata &) = delete;
+
+ unsigned as_uint() const {
+ assert(value_type == UINT);
+ return uint_value;
+ }
+
+ signed as_sint() const {
+ assert(value_type == SINT);
+ return sint_value;
+ }
+
+ const std::string &as_string() const {
+ assert(value_type == STRING);
+ return string_value;
+ }
+
+ double as_double() const {
+ assert(value_type == DOUBLE);
+ return double_value;
+ }
+};
+
+typedef std::map<std::string, metadata> metadata_map;
+
struct module {
module() {}
virtual ~module() {}
@@ -661,15 +717,16 @@ struct module {
module(const module &) = delete;
module &operator=(const module &) = delete;
- virtual void eval() = 0;
+ virtual bool eval() = 0;
virtual bool commit() = 0;
size_t step() {
size_t deltas = 0;
+ bool converged = false;
do {
- eval();
+ converged = eval();
deltas++;
- } while (commit());
+ } while (commit() && !converged);
return deltas;
}
};
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index cc20f17fc..7e24468c0 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -113,6 +113,9 @@ struct EdifBackend : public Backend {
log(" -attrprop\n");
log(" create EDIF properties for cell attributes\n");
log("\n");
+ log(" -keep\n");
+ log(" create extra KEEP nets by allowing a cell to drive multiple nets.\n");
+ log("\n");
log(" -pvector {par|bra|ang}\n");
log(" sets the delimiting character for module port rename clauses to\n");
log(" parentheses, square brackets, or angle brackets.\n");
@@ -130,7 +133,7 @@ struct EdifBackend : public Backend {
bool port_rename = false;
bool attr_properties = false;
std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
- bool nogndvcc = false, gndvccy = false;
+ bool nogndvcc = false, gndvccy = false, keepmode = false;
CellTypes ct(design);
EdifNames edif_names;
@@ -153,6 +156,10 @@ struct EdifBackend : public Backend {
attr_properties = true;
continue;
}
+ if (args[argidx] == "-keep") {
+ keepmode = true;
+ continue;
+ }
if (args[argidx] == "-pvector" && argidx+1 < args.size()) {
std::string parray;
port_rename = true;
@@ -337,6 +344,71 @@ struct EdifBackend : public Backend {
*f << stringf(" (view VIEW_NETLIST\n");
*f << stringf(" (viewType NETLIST)\n");
*f << stringf(" (interface\n");
+
+ for (auto cell : module->cells()) {
+ for (auto &conn : cell->connections())
+ if (cell->output(conn.first))
+ sigmap.add(conn.second);
+ }
+
+ for (auto wire : module->wires())
+ for (auto b1 : SigSpec(wire))
+ {
+ auto b2 = sigmap(b1);
+
+ if (b1 == b2 || !b2.wire)
+ continue;
+
+ log_assert(b1.wire != nullptr);
+
+ Wire *w1 = b1.wire;
+ Wire *w2 = b2.wire;
+
+ {
+ int c1 = w1->get_bool_attribute(ID::keep);
+ int c2 = w2->get_bool_attribute(ID::keep);
+
+ if (c1 > c2) goto promote;
+ if (c1 < c2) goto nopromote;
+ }
+
+ {
+ int c1 = w1->name[0] == '\\';
+ int c2 = w2->name[0] == '\\';
+
+ if (c1 > c2) goto promote;
+ if (c1 < c2) goto nopromote;
+ }
+
+ {
+ auto count_nontrivial_attr = [](Wire *w) {
+ int count = w->attributes.size();
+ count -= w->attributes.count(ID::src);
+ count -= w->attributes.count(ID::unused_bits);
+ return count;
+ };
+
+ int c1 = count_nontrivial_attr(w1);
+ int c2 = count_nontrivial_attr(w2);
+
+ if (c1 > c2) goto promote;
+ if (c1 < c2) goto nopromote;
+ }
+
+ {
+ int c1 = w1->port_id ? INT_MAX - w1->port_id : 0;
+ int c2 = w2->port_id ? INT_MAX - w2->port_id : 0;
+
+ if (c1 > c2) goto promote;
+ if (c1 < c2) goto nopromote;
+ }
+
+ nopromote:
+ if (0)
+ promote:
+ sigmap.add(b1);
+ }
+
for (auto wire : module->wires()) {
if (wire->port_id == 0)
continue;
@@ -369,12 +441,15 @@ struct EdifBackend : public Backend {
}
}
}
+
*f << stringf(" )\n");
*f << stringf(" (contents\n");
+
if (!nogndvcc) {
*f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
*f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
}
+
for (auto cell : module->cells()) {
*f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
*f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
@@ -412,6 +487,7 @@ struct EdifBackend : public Backend {
}
}
}
+
for (auto &it : net_join_db) {
RTLIL::SigBit sig = it.first;
if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) {
@@ -440,7 +516,7 @@ struct EdifBackend : public Backend {
}
*f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
for (auto &ref : it.second)
- *f << stringf(" %s\n", ref.first.c_str());
+ *f << stringf(" %s\n", ref.first.c_str());
if (sig.wire == NULL) {
if (nogndvcc)
log_error("Design contains constant nodes (map with \"hilomap\" first).\n");
@@ -455,30 +531,48 @@ struct EdifBackend : public Backend {
add_prop(p.first, p.second);
*f << stringf("\n )\n");
}
- for (auto wire : module->wires()) {
+
+ for (auto wire : module->wires())
+ {
if (!wire->get_bool_attribute(ID::keep))
continue;
- for(int i = 0; i < wire->width; i++) {
+
+ for(int i = 0; i < wire->width; i++)
+ {
SigBit raw_sig = RTLIL::SigSpec(wire, i);
SigBit mapped_sig = sigmap(raw_sig);
+
if (raw_sig == mapped_sig || net_join_db.count(mapped_sig) == 0)
continue;
+
std::string netname = log_signal(raw_sig);
for (size_t i = 0; i < netname.size(); i++)
if (netname[i] == ' ' || netname[i] == '\\')
netname.erase(netname.begin() + i--);
- *f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
- auto &refs = net_join_db.at(mapped_sig);
- for (auto &ref : refs)
- if (ref.second)
- *f << stringf(" %s\n", ref.first.c_str());
- *f << stringf(" )");
- if (attr_properties && raw_sig.wire != NULL)
- for (auto &p : raw_sig.wire->attributes)
- add_prop(p.first, p.second);
- *f << stringf("\n )\n");
+
+ if (keepmode)
+ {
+ *f << stringf(" (net %s (joined\n", EDIF_DEF(netname));
+
+ auto &refs = net_join_db.at(mapped_sig);
+ for (auto &ref : refs)
+ if (ref.second)
+ *f << stringf(" %s\n", ref.first.c_str());
+ *f << stringf(" )");
+
+ if (attr_properties && raw_sig.wire != NULL)
+ for (auto &p : raw_sig.wire->attributes)
+ add_prop(p.first, p.second);
+
+ *f << stringf("\n )\n");
+ }
+ else
+ {
+ log_warning("Ignoring conflicting 'keep' property on net %s. Use -keep to generate the extra net nevertheless.\n", EDIF_DEF(netname));
+ }
}
}
+
*f << stringf(" )\n");
*f << stringf(" )\n");
*f << stringf(" )\n");
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index fd7f20cc6..40d05a036 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -306,17 +306,8 @@ struct FirrtlWorker
// If this is a parameterized module, its parent module is encoded in the cell type
if (cell->type.begins_with("$paramod"))
{
- std::string::iterator it;
- for (it = cell_type.begin(); it < cell_type.end(); it++)
- {
- switch (*it) {
- case '\\': /* FALL_THROUGH */
- case '=': /* FALL_THROUGH */
- case '\'': /* FALL_THROUGH */
- case '$': instanceOf.append("_"); break;
- default: instanceOf.append(1, *it); break;
- }
- }
+ log_assert(cell->has_attribute(ID::hdlname));
+ instanceOf = cell->get_string_attribute(ID::hdlname);
}
else
{
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index 5445fad90..6e3882d2d 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -290,8 +290,16 @@ void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
if (!module->avail_parameters.empty()) {
if (only_selected)
f << stringf("\n");
- for (auto &p : module->avail_parameters)
- f << stringf("%s" " parameter %s\n", indent.c_str(), p.c_str());
+ for (const auto &p : module->avail_parameters) {
+ const auto &it = module->parameter_default_values.find(p);
+ if (it == module->parameter_default_values.end()) {
+ f << stringf("%s" " parameter %s\n", indent.c_str(), p.c_str());
+ } else {
+ f << stringf("%s" " parameter %s ", indent.c_str(), p.c_str());
+ dump_const(f, it->second);
+ f << stringf("\n");
+ }
+ }
}
}
diff --git a/backends/json/json.cc b/backends/json/json.cc
index 1da23bb7d..1a8b757ef 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -141,6 +141,12 @@ struct JsonWriter
write_parameters(module->attributes, /*for_module=*/true);
f << stringf("\n },\n");
+ if (module->parameter_default_values.size()) {
+ f << stringf(" \"parameter_default_values\": {");
+ write_parameters(module->parameter_default_values, /*for_module=*/true);
+ f << stringf("\n },\n");
+ }
+
f << stringf(" \"ports\": {");
bool first = true;
for (auto n : module->ports) {
@@ -310,6 +316,10 @@ struct JsonBackend : public Backend {
log(" <attribute_name>: <attribute_value>,\n");
log(" ...\n");
log(" },\n");
+ log(" \"parameter_default_values\": {\n");
+ log(" <parameter_name>: <parameter_value>,\n");
+ log(" ...\n");
+ log(" },\n");
log(" \"ports\": {\n");
log(" <port_name>: <port_details>,\n");
log(" ...\n");
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 03:03:00 +0000