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-rw-r--r--backends/btor/btor.cc1
-rw-r--r--backends/firrtl/firrtl.cc1
-rw-r--r--backends/smt2/smt2.cc1
-rw-r--r--backends/smv/smv.cc1
-rw-r--r--backends/verilog/verilog_backend.cc49
5 files changed, 42 insertions, 11 deletions
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 06de71018..8368ab82d 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -1417,6 +1417,7 @@ struct BtorBackend : public Backend {
log_push();
Pass::call(design, "bmuxmap");
Pass::call(design, "demuxmap");
+ Pass::call(design, "bwmuxmap");
log_pop();
size_t argidx;
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 76ba77abb..e483117d1 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -1215,6 +1215,7 @@ struct FirrtlBackend : public Backend {
Pass::call(design, "pmuxtree");
Pass::call(design, "bmuxmap");
Pass::call(design, "demuxmap");
+ Pass::call(design, "bwmuxmap");
namecache.clear();
autoid_counter = 0;
diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index 7434b13da..fe50ca7f6 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -1744,6 +1744,7 @@ struct Smt2Backend : public Backend {
log_push();
Pass::call(design, "bmuxmap");
Pass::call(design, "demuxmap");
+ Pass::call(design, "bwmuxmap");
log_pop();
size_t argidx;
diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc
index 7d4f94adc..49c2cc7a6 100644
--- a/backends/smv/smv.cc
+++ b/backends/smv/smv.cc
@@ -744,6 +744,7 @@ struct SmvBackend : public Backend {
log_push();
Pass::call(design, "bmuxmap");
Pass::call(design, "demuxmap");
+ Pass::call(design, "bwmuxmap");
log_pop();
size_t argidx;
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index e60ebc70e..0a9c0590e 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -35,7 +35,7 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog, simple_lhs;
+bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog, simple_lhs, noparallelcase;
int auto_name_counter, auto_name_offset, auto_name_digits, extmem_counter;
std::map<RTLIL::IdString, int> auto_name_map;
std::set<RTLIL::IdString> reg_wires;
@@ -1209,7 +1209,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($modfloor))
{
// wire truncated = $signed(A) % $signed(B);
- // assign Y = (A[-1] == B[-1]) || truncated == 0 ? truncated : $signed(B) + $signed(truncated);
+ // assign Y = (A[-1] == B[-1]) || truncated == 0 ? $signed(truncated) : $signed(B) + $signed(truncated);
if (cell->getParam(ID::A_SIGNED).as_bool() && cell->getParam(ID::B_SIGNED).as_bool()) {
SigSpec sig_a = cell->getPort(ID::A);
@@ -1229,7 +1229,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
dump_sigspec(f, sig_a.extract(sig_a.size()-1));
f << stringf(" == ");
dump_sigspec(f, sig_b.extract(sig_b.size()-1));
- f << stringf(") || %s == 0 ? %s : ", temp_id.c_str(), temp_id.c_str());
+ f << stringf(") || %s == 0 ? $signed(%s) : ", temp_id.c_str(), temp_id.c_str());
dump_cell_expr_port(f, cell, "B", true);
f << stringf(" + $signed(%s);\n", temp_id.c_str());
return true;
@@ -1314,24 +1314,38 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" " input [%d:0] s;\n", indent.c_str(), s_width-1);
dump_attributes(f, indent + " ", cell->attributes);
- if (!noattr)
- f << stringf("%s" " (* parallel_case *)\n", indent.c_str());
- f << stringf("%s" " casez (s)", indent.c_str());
- f << stringf(noattr ? " // synopsys parallel_case\n" : "\n");
+ if (noparallelcase)
+ f << stringf("%s" " case (s)\n", indent.c_str());
+ else {
+ if (!noattr)
+ f << stringf("%s" " (* parallel_case *)\n", indent.c_str());
+ f << stringf("%s" " casez (s)", indent.c_str());
+ f << stringf(noattr ? " // synopsys parallel_case\n" : "\n");
+ }
for (int i = 0; i < s_width; i++)
{
f << stringf("%s" " %d'b", indent.c_str(), s_width);
for (int j = s_width-1; j >= 0; j--)
- f << stringf("%c", j == i ? '1' : '?');
+ f << stringf("%c", j == i ? '1' : noparallelcase ? '0' : '?');
f << stringf(":\n");
f << stringf("%s" " %s = b[%d:%d];\n", indent.c_str(), func_name.c_str(), (i+1)*width-1, i*width);
}
- f << stringf("%s" " default:\n", indent.c_str());
+ if (noparallelcase) {
+ f << stringf("%s" " %d'b", indent.c_str(), s_width);
+ for (int j = s_width-1; j >= 0; j--)
+ f << '0';
+ f << stringf(":\n");
+ } else
+ f << stringf("%s" " default:\n", indent.c_str());
f << stringf("%s" " %s = a;\n", indent.c_str(), func_name.c_str());
+ if (noparallelcase) {
+ f << stringf("%s" " default:\n", indent.c_str());
+ f << stringf("%s" " %s = %d'bx;\n", indent.c_str(), func_name.c_str(), width);
+ }
f << stringf("%s" " endcase\n", indent.c_str());
f << stringf("%s" "endfunction\n", indent.c_str());
@@ -2136,6 +2150,11 @@ struct VerilogBackend : public Backend {
log(" without this option all internal cells are converted to Verilog\n");
log(" expressions.\n");
log("\n");
+ log(" -noparallelcase\n");
+ log(" With this option no parallel_case attributes are used. Instead, a case\n");
+ log(" statement that assigns don't-care values for priority dependent inputs\n");
+ log(" is generated.\n");
+ log("\n");
log(" -siminit\n");
log(" add initial statements with hierarchical refs to initialize FFs when\n");
log(" in -noexpr mode.\n");
@@ -2211,6 +2230,7 @@ struct VerilogBackend : public Backend {
decimal = false;
siminit = false;
simple_lhs = false;
+ noparallelcase = false;
auto_prefix = "";
bool blackboxes = false;
@@ -2246,6 +2266,10 @@ struct VerilogBackend : public Backend {
noexpr = true;
continue;
}
+ if (arg == "-noparallelcase") {
+ noparallelcase = true;
+ continue;
+ }
if (arg == "-nodec") {
nodec = true;
continue;
@@ -2302,8 +2326,11 @@ struct VerilogBackend : public Backend {
}
log_push();
- Pass::call(design, "bmuxmap");
- Pass::call(design, "demuxmap");
+ if (!noexpr) {
+ Pass::call(design, "bmuxmap");
+ Pass::call(design, "demuxmap");
+ Pass::call(design, "bwmuxmap");
+ }
Pass::call(design, "clean_zerowidth");
log_pop();
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 10:55:48 +0000