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-rw-r--r--backends/firrtl/firrtl.cc6
-rw-r--r--backends/rtlil/rtlil_backend.cc2
-rw-r--r--backends/smt2/smt2.cc5
-rw-r--r--backends/verilog/verilog_backend.cc1
4 files changed, 11 insertions, 3 deletions
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index d68c52563..eb30ab4b9 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -346,6 +346,12 @@ void emit_elaborated_extmodules(RTLIL::Design *design, std::ostream &f)
{
// Find the module corresponding to this instance.
auto modInstance = design->module(cell->type);
+ // Ensure that we actually have a module instance
+ if (modInstance == nullptr) {
+ log_error("Unknown cell type %s\n", cell->type.c_str());
+ return;
+ }
+
bool modIsBlackbox = modInstance->get_blackbox_attribute();
if (modIsBlackbox)
diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc
index 7c7e26a93..574eb3aaa 100644
--- a/backends/rtlil/rtlil_backend.cc
+++ b/backends/rtlil/rtlil_backend.cc
@@ -51,7 +51,7 @@ void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi
}
}
f << stringf("%d'", width);
- if (data.is_fully_undef()) {
+ if (data.is_fully_undef_x_only()) {
f << "x";
} else {
for (int i = offset+width-1; i >= offset; i--) {
diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index 1ab39a405..48da3f4be 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -462,7 +462,10 @@ struct Smt2Worker
int width = GetSize(sig_y);
if (type == 's' || type == 'S' || type == 'd' || type == 'b') {
- width = max(width, GetSize(cell->getPort(ID::A)));
+ if (type == 'b')
+ width = GetSize(cell->getPort(ID::A));
+ else
+ width = max(width, GetSize(cell->getPort(ID::A)));
if (cell->hasPort(ID::B))
width = max(width, GetSize(cell->getPort(ID::B)));
}
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 0a9c0590e..3da168960 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -2329,7 +2329,6 @@ struct VerilogBackend : public Backend {
if (!noexpr) {
Pass::call(design, "bmuxmap");
Pass::call(design, "demuxmap");
- Pass::call(design, "bwmuxmap");
}
Pass::call(design, "clean_zerowidth");
log_pop();