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-rw-r--r--backends/blif/blif.cc26
-rw-r--r--backends/edif/edif.cc41
-rw-r--r--backends/firrtl/firrtl.cc1
-rw-r--r--backends/ilang/ilang_backend.cc12
-rw-r--r--backends/intersynth/intersynth.cc41
-rw-r--r--backends/smt2/smt2.cc24
-rw-r--r--backends/smt2/smtbmc.py14
-rw-r--r--backends/smt2/smtio.py16
-rw-r--r--backends/spice/spice.cc22
-rw-r--r--backends/verilog/verilog_backend.cc41
10 files changed, 127 insertions, 111 deletions
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index b6e38c16c..4bdaf7a7f 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -138,9 +138,9 @@ struct BlifDumper
{
if (!config->gates_mode)
return "subckt";
- if (!design->modules_.count(RTLIL::escape_id(cell_type)))
+ if (design->module(RTLIL::escape_id(cell_type)) == nullptr)
return "gate";
- if (design->modules_.at(RTLIL::escape_id(cell_type))->get_blackbox_attribute())
+ if (design->module(RTLIL::escape_id(cell_type))->get_blackbox_attribute())
return "gate";
return "subckt";
}
@@ -148,7 +148,7 @@ struct BlifDumper
void dump_params(const char *command, dict<IdString, Const> &params)
{
for (auto &param : params) {
- f << stringf("%s %s ", command, RTLIL::id2cstr(param.first));
+ f << stringf("%s %s ", command, log_id(param.first));
if (param.second.flags & RTLIL::CONST_FLAG_STRING) {
std::string str = param.second.decode_string();
f << stringf("\"");
@@ -172,8 +172,7 @@ struct BlifDumper
std::map<int, RTLIL::Wire*> inputs, outputs;
- for (auto &wire_it : module->wires_) {
- RTLIL::Wire *wire = wire_it.second;
+ for (auto wire : module->wires()) {
if (wire->port_input)
inputs[wire->port_id] = wire;
if (wire->port_output)
@@ -229,10 +228,8 @@ struct BlifDumper
f << stringf(".names $undef\n");
}
- for (auto &cell_it : module->cells_)
+ for (auto cell : module->cells())
{
- RTLIL::Cell *cell = cell_it.second;
-
if (config->unbuf_types.count(cell->type)) {
auto portnames = config->unbuf_types.at(cell->type);
f << stringf(".names %s %s\n1 1\n",
@@ -649,25 +646,24 @@ struct BlifBackend : public Backend {
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
- for (auto & mod_it:design->modules_)
- if (mod_it.second->get_bool_attribute("\\top"))
- top_module_name = mod_it.first.str();
+ for (auto module : design->modules())
+ if (module->get_bool_attribute("\\top"))
+ top_module_name = module->name.str();
*f << stringf("# Generated by %s\n", yosys_version_str);
std::vector<RTLIL::Module*> mod_list;
design->sort();
- for (auto module_it : design->modules_)
+ for (auto module : design->modules())
{
- RTLIL::Module *module = module_it.second;
if (module->get_blackbox_attribute() && !config.blackbox_mode)
continue;
if (module->processes.size() != 0)
- log_error("Found unmapped processes in module %s: unmapped processes are not supported in BLIF backend!\n", RTLIL::id2cstr(module->name));
+ log_error("Found unmapped processes in module %s: unmapped processes are not supported in BLIF backend!\n", log_id(module->name));
if (module->memories.size() != 0)
- log_error("Found unmapped memories in module %s: unmapped memories are not supported in BLIF backend!\n", RTLIL::id2cstr(module->name));
+ log_error("Found unmapped memories in module %s: unmapped memories are not supported in BLIF backend!\n", log_id(module->name));
if (module->name == RTLIL::escape_id(top_module_name)) {
BlifDumper::dump(*f, module, design, config);
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 199560ad0..cb1b4c284 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -171,13 +171,12 @@ struct EdifBackend : public Backend {
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
- for (auto & mod_it:design->modules_)
- if (mod_it.second->get_bool_attribute("\\top"))
- top_module_name = mod_it.first.str();
+ for (auto module : design->modules())
+ if (module->get_bool_attribute("\\top"))
+ top_module_name = module->name.str();
- for (auto module_it : design->modules_)
+ for (auto module : design->modules())
{
- RTLIL::Module *module = module_it.second;
if (module->get_blackbox_attribute())
continue;
@@ -185,14 +184,13 @@ struct EdifBackend : public Backend {
top_module_name = module->name.str();
if (module->processes.size() != 0)
- log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
+ log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", log_id(module->name));
if (module->memories.size() != 0)
- log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
+ log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", log_id(module->name));
- for (auto cell_it : module->cells_)
+ for (auto cell : module->cells())
{
- RTLIL::Cell *cell = cell_it.second;
- if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_blackbox_attribute()) {
+ if (design->module(cell->type) == nullptr || design->module(cell->type)->get_blackbox_attribute()) {
lib_cell_ports[cell->type];
for (auto p : cell->connections())
lib_cell_ports[cell->type][p.first] = GetSize(p.second);
@@ -277,11 +275,11 @@ struct EdifBackend : public Backend {
// extract module dependencies
std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
- for (auto &mod_it : design->modules_) {
- module_deps[mod_it.second] = std::set<RTLIL::Module*>();
- for (auto &cell_it : mod_it.second->cells_)
- if (design->modules_.count(cell_it.second->type) > 0)
- module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
+ for (auto module : design->modules()) {
+ module_deps[module] = std::set<RTLIL::Module*>();
+ for (auto cell : module->cells())
+ if (design->module(cell->type) != nullptr)
+ module_deps[module].insert(design->module(cell->type));
}
// simple good-enough topological sort
@@ -292,12 +290,12 @@ struct EdifBackend : public Backend {
for (auto &dep : it.second)
if (module_deps.count(dep) > 0)
goto not_ready_yet;
- // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
+ // log("Next in topological sort: %s\n", log_id(it.first->name));
sorted_modules.push_back(it.first);
not_ready_yet:;
}
if (sorted_modules_idx == sorted_modules.size())
- log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name));
+ log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", log_id(module_deps.begin()->first->name));
while (sorted_modules_idx < sorted_modules.size())
module_deps.erase(sorted_modules.at(sorted_modules_idx++));
}
@@ -339,8 +337,7 @@ struct EdifBackend : public Backend {
*f << stringf(" (view VIEW_NETLIST\n");
*f << stringf(" (viewType NETLIST)\n");
*f << stringf(" (interface\n");
- for (auto &wire_it : module->wires_) {
- RTLIL::Wire *wire = wire_it.second;
+ for (auto wire : module->wires()) {
if (wire->port_id == 0)
continue;
const char *dir = "INOUT";
@@ -378,8 +375,7 @@ struct EdifBackend : public Backend {
*f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
*f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
}
- for (auto &cell_it : module->cells_) {
- RTLIL::Cell *cell = cell_it.second;
+ for (auto cell : module->cells()) {
*f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
*f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
@@ -459,8 +455,7 @@ struct EdifBackend : public Backend {
add_prop(p.first, p.second);
*f << stringf("\n )\n");
}
- for (auto &wire_it : module->wires_) {
- RTLIL::Wire *wire = wire_it.second;
+ for (auto wire : module->wires()) {
if (!wire->get_bool_attribute(ID::keep))
continue;
for(int i = 0; i < wire->width; i++) {
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 87db0edf7..22aa686a7 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -25,7 +25,6 @@
#include "kernel/log.h"
#include <algorithm>
#include <string>
-#include <regex>
#include <vector>
#include <cmath>
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index e06786220..5445fad90 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -358,10 +358,10 @@ void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
if (!flag_m) {
int count_selected_mods = 0;
- for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
- if (design->selected_whole_module(it->first))
+ for (auto module : design->modules()) {
+ if (design->selected_whole_module(module->name))
flag_m = true;
- if (design->selected(it->second))
+ if (design->selected(module))
count_selected_mods++;
}
if (count_selected_mods > 1)
@@ -374,11 +374,11 @@ void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
f << stringf("autoidx %d\n", autoidx);
}
- for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
- if (!only_selected || design->selected(it->second)) {
+ for (auto module : design->modules()) {
+ if (!only_selected || design->selected(module)) {
if (only_selected)
f << stringf("\n");
- dump_module(f, "", it->second, design, only_selected, flag_m, flag_n);
+ dump_module(f, "", module, design, only_selected, flag_m, flag_n);
}
}
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 809a0fa09..31dce1cca 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -122,70 +122,67 @@ struct IntersynthBackend : public Backend {
for (auto lib : libs)
ct.setup_design(lib);
- for (auto module_it : design->modules_)
+ for (auto module : design->modules())
{
- RTLIL::Module *module = module_it.second;
SigMap sigmap(module);
if (module->get_blackbox_attribute())
continue;
- if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells_.size() == 0)
+ if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells().size() == 0)
continue;
if (selected && !design->selected_whole_module(module->name)) {
if (design->selected_module(module->name))
- log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(module->name));
+ log_cmd_error("Can't handle partially selected module %s!\n", log_id(module->name));
continue;
}
- log("Generating netlist %s.\n", RTLIL::id2cstr(module->name));
+ log("Generating netlist %s.\n", log_id(module->name));
if (module->memories.size() != 0 || module->processes.size() != 0)
log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n");
std::set<std::string> constcells_code;
- netlists_code += stringf("# Netlist of module %s\n", RTLIL::id2cstr(module->name));
- netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name));
+ netlists_code += stringf("# Netlist of module %s\n", log_id(module->name));
+ netlists_code += stringf("netlist %s\n", log_id(module->name));
// Module Ports: "std::set<string> celltypes_code" prevents duplicate top level ports
- for (auto wire_it : module->wires_) {
- RTLIL::Wire *wire = wire_it.second;
+ for (auto wire : module->wires()) {
if (wire->port_input || wire->port_output) {
celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
- RTLIL::id2cstr(wire->name), wire->width, wire->port_input ? "*" : "",
- wire->port_input ? "input" : "output", RTLIL::id2cstr(wire->name), wire->width, RTLIL::id2cstr(wire->name)));
- netlists_code += stringf("node %s %s PORT %s\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(wire->name),
+ log_id(wire->name), wire->width, wire->port_input ? "*" : "",
+ wire->port_input ? "input" : "output", log_id(wire->name), wire->width, log_id(wire->name)));
+ netlists_code += stringf("node %s %s PORT %s\n", log_id(wire->name), log_id(wire->name),
netname(conntypes_code, celltypes_code, constcells_code, sigmap(wire)).c_str());
}
}
// Submodules: "std::set<string> celltypes_code" prevents duplicate cell types
- for (auto cell_it : module->cells_)
+ for (auto cell : module->cells())
{
- RTLIL::Cell *cell = cell_it.second;
std::string celltype_code, node_code;
if (!ct.cell_known(cell->type))
- log_error("Found unknown cell type %s in module!\n", RTLIL::id2cstr(cell->type));
+ log_error("Found unknown cell type %s in module!\n", log_id(cell->type));
- celltype_code = stringf("celltype %s", RTLIL::id2cstr(cell->type));
- node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
+ celltype_code = stringf("celltype %s", log_id(cell->type));
+ node_code = stringf("node %s %s", log_id(cell->name), log_id(cell->type));
for (auto &port : cell->connections()) {
RTLIL::SigSpec sig = sigmap(port.second);
if (sig.size() != 0) {
conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));
- celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first));
- node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
+ celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", log_id(port.first));
+ node_code += stringf(" %s %s", log_id(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
}
}
for (auto &param : cell->parameters) {
- celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), RTLIL::id2cstr(param.first));
+ celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), log_id(param.first));
if (param.second.bits.size() != 32) {
- node_code += stringf(" %s '", RTLIL::id2cstr(param.first));
+ node_code += stringf(" %s '", log_id(param.first));
for (int i = param.second.bits.size()-1; i >= 0; i--)
node_code += param.second.bits[i] == State::S1 ? "1" : "0";
} else
- node_code += stringf(" %s 0x%x", RTLIL::id2cstr(param.first), param.second.as_int());
+ node_code += stringf(" %s 0x%x", log_id(param.first), param.second.as_int());
}
celltypes_code.insert(celltype_code + "\n");
diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index 081dcda99..eb4826051 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -536,6 +536,14 @@ struct Smt2Worker
if (cell->attributes.count("\\reg"))
infostr += " " + cell->attributes.at("\\reg").decode_string();
decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort("\\Y")), infostr.c_str()));
+ if (cell->getPort("\\Y").is_wire() && cell->getPort("\\Y").as_wire()->get_bool_attribute("\\maximize")){
+ decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter));
+ log("Wire %s is maximized\n", cell->getPort("\\Y").as_wire()->name.str().c_str());
+ }
+ else if (cell->getPort("\\Y").is_wire() && cell->getPort("\\Y").as_wire()->get_bool_attribute("\\minimize")){
+ decls.push_back(stringf("; yosys-smt2-minimize %s#%d\n", get_id(module), idcounter));
+ log("Wire %s is minimized\n", cell->getPort("\\Y").as_wire()->name.str().c_str());
+ }
makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Y")), log_signal(cell->getPort("\\Y")));
if (cell->type == "$anyseq")
ex_input_eq.push_back(stringf(" (= (|%s#%d| state) (|%s#%d| other_state))", get_id(module), idcounter, get_id(module), idcounter));
@@ -1386,7 +1394,7 @@ struct Smt2Backend : public Backend {
log("\n");
log("For this proof we create the following template (test.tpl).\n");
log("\n");
- log(" ; we need QF_UFBV for this poof\n");
+ log(" ; we need QF_UFBV for this proof\n");
log(" (set-logic QF_UFBV)\n");
log("\n");
log(" ; insert the auto-generated code here\n");
@@ -1500,11 +1508,11 @@ struct Smt2Backend : public Backend {
// extract module dependencies
std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
- for (auto &mod_it : design->modules_) {
- module_deps[mod_it.second] = std::set<RTLIL::Module*>();
- for (auto &cell_it : mod_it.second->cells_)
- if (design->modules_.count(cell_it.second->type) > 0)
- module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
+ for (auto mod : design->modules()) {
+ module_deps[mod] = std::set<RTLIL::Module*>();
+ for (auto cell : mod->cells())
+ if (design->has(cell->type))
+ module_deps[mod].insert(design->module(cell->type));
}
// simple good-enough topological sort
@@ -1515,12 +1523,12 @@ struct Smt2Backend : public Backend {
for (auto &dep : it.second)
if (module_deps.count(dep) > 0)
goto not_ready_yet;
- // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name));
+ // log("Next in topological sort: %s\n", log_id(it.first->name));
sorted_modules.push_back(it.first);
not_ready_yet:;
}
if (sorted_modules_idx == sorted_modules.size())
- log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name));
+ log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", log_id(module_deps.begin()->first->name));
while (sorted_modules_idx < sorted_modules.size())
module_deps.erase(sorted_modules.at(sorted_modules_idx++));
}
diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py
index 3d6d3e1b3..630464419 100644
--- a/backends/smt2/smtbmc.py
+++ b/backends/smt2/smtbmc.py
@@ -1158,6 +1158,8 @@ def smt_forall_assert():
global asserts_cache_dirty
asserts_cache_dirty = False
+ assert (len(smt.modinfo[topmod].maximize) + len(smt.modinfo[topmod].minimize) <= 1)
+
def make_assert_expr(asserts_cache):
expr = list()
for lst in asserts_cache:
@@ -1236,6 +1238,18 @@ def smt_forall_assert():
smt.write("".join(assert_expr))
+ if len(smt.modinfo[topmod].maximize) > 0:
+ for s in states:
+ if s in used_states_db:
+ smt.write("(maximize (|%s| %s))\n" % (smt.modinfo[topmod].maximize.copy().pop(), s))
+ break
+
+ if len(smt.modinfo[topmod].minimize) > 0:
+ for s in states:
+ if s in used_states_db:
+ smt.write("(minimize (|%s| %s))\n" % (smt.modinfo[topmod].minimize.copy().pop(), s))
+ break
+
def smt_push():
global asserts_cache_dirty
asserts_cache_dirty = True
diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py
index 34bf7ef38..69f59df79 100644
--- a/backends/smt2/smtio.py
+++ b/backends/smt2/smtio.py
@@ -101,6 +101,8 @@ class SmtModInfo:
self.cells = dict()
self.asserts = dict()
self.covers = dict()
+ self.maximize = set()
+ self.minimize = set()
self.anyconsts = dict()
self.anyseqs = dict()
self.allconsts = dict()
@@ -502,6 +504,12 @@ class SmtIo:
if fields[1] == "yosys-smt2-cover":
self.modinfo[self.curmod].covers["%s_c %s" % (self.curmod, fields[2])] = fields[3]
+ if fields[1] == "yosys-smt2-maximize":
+ self.modinfo[self.curmod].maximize.add(fields[2])
+
+ if fields[1] == "yosys-smt2-minimize":
+ self.modinfo[self.curmod].minimize.add(fields[2])
+
if fields[1] == "yosys-smt2-anyconst":
self.modinfo[self.curmod].anyconsts[fields[2]] = (fields[4], None if len(fields) <= 5 else fields[5])
self.modinfo[self.curmod].asize[fields[2]] = int(fields[3])
@@ -696,7 +704,13 @@ class SmtIo:
if msg is not None:
print("%s waiting for solver (%s)" % (self.timestamp(), msg), flush=True)
- result = self.read()
+ if self.forall:
+ result = self.read()
+ while result not in ["sat", "unsat", "unknown"]:
+ print("%s %s: %s" % (self.timestamp(), self.solver, result))
+ result = self.read()
+ else:
+ result = self.read()
if self.debug_file:
print("(set-info :status %s)" % result, file=self.debug_file)
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 6738a4bbd..9b603a8c5 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -70,14 +70,13 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
idict<IdString, 1> inums;
int cell_counter = 0, conn_counter = 0, nc_counter = 0;
- for (auto &cell_it : module->cells_)
+ for (auto cell : module->cells())
{
- RTLIL::Cell *cell = cell_it.second;
f << stringf("X%d", cell_counter++);
std::vector<RTLIL::SigSpec> port_sigs;
- if (design->modules_.count(cell->type) == 0)
+ if (design->module(cell->type) == nullptr)
{
log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
log_id(cell->type), log_id(module), log_id(cell));
@@ -88,11 +87,10 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
}
else
{
- RTLIL::Module *mod = design->modules_.at(cell->type);
+ RTLIL::Module *mod = design->module(cell->type);
std::vector<RTLIL::Wire*> ports;
- for (auto wire_it : mod->wires_) {
- RTLIL::Wire *wire = wire_it.second;
+ for (auto wire : mod->wires()) {
if (wire->port_id == 0)
continue;
while (int(ports.size()) < wire->port_id)
@@ -202,16 +200,15 @@ struct SpiceBackend : public Backend {
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
- for (auto & mod_it:design->modules_)
- if (mod_it.second->get_bool_attribute("\\top"))
- top_module_name = mod_it.first.str();
+ for (auto module : design->modules())
+ if (module->get_bool_attribute("\\top"))
+ top_module_name = module->name.str();
*f << stringf("* SPICE netlist generated by %s\n", yosys_version_str);
*f << stringf("\n");
- for (auto module_it : design->modules_)
+ for (auto module : design->modules())
{
- RTLIL::Module *module = module_it.second;
if (module->get_blackbox_attribute())
continue;
@@ -226,8 +223,7 @@ struct SpiceBackend : public Backend {
}
std::vector<RTLIL::Wire*> ports;
- for (auto wire_it : module->wires_) {
- RTLIL::Wire *wire = wire_it.second;
+ for (auto wire : module->wires()) {
if (wire->port_id == 0)
continue;
while (int(ports.size()) < wire->port_id)
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 19541f1c4..e0fd201e1 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -73,12 +73,12 @@ void reset_auto_counter(RTLIL::Module *module)
reset_auto_counter_id(module->name, false);
- for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it)
- reset_auto_counter_id(it->second->name, true);
+ for (auto w : module->wires())
+ reset_auto_counter_id(w->name, true);
- for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it) {
- reset_auto_counter_id(it->second->name, true);
- reset_auto_counter_id(it->second->type, false);
+ for (auto cell : module->cells()) {
+ reset_auto_counter_id(cell->name, true);
+ reset_auto_counter_id(cell->type, false);
}
for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
@@ -1719,9 +1719,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
if (!noexpr)
{
std::set<std::pair<RTLIL::Wire*,int>> reg_bits;
- for (auto &it : module->cells_)
+ for (auto cell : module->cells())
{
- RTLIL::Cell *cell = it.second;
if (!reg_ct.count(cell->type) || !cell->hasPort("\\Q"))
continue;
@@ -1734,9 +1733,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
reg_bits.insert(std::pair<RTLIL::Wire*,int>(chunk.wire, chunk.offset+i));
}
}
- for (auto &it : module->wires_)
+ for (auto wire : module->wires())
{
- RTLIL::Wire *wire = it.second;
for (int i = 0; i < wire->width; i++)
if (reg_bits.count(std::pair<RTLIL::Wire*,int>(wire, i)) == 0)
goto this_wire_aint_reg;
@@ -1751,8 +1749,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
bool keep_running = true;
for (int port_id = 1; keep_running; port_id++) {
keep_running = false;
- for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it) {
- RTLIL::Wire *wire = it->second;
+ for (auto wire : module->wires()) {
if (wire->port_id == port_id) {
if (port_id != 1)
f << stringf(", ");
@@ -1764,14 +1761,14 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
}
f << stringf(");\n");
- for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it)
- dump_wire(f, indent + " ", it->second);
+ for (auto w : module->wires())
+ dump_wire(f, indent + " ", w);
for (auto it = module->memories.begin(); it != module->memories.end(); ++it)
dump_memory(f, indent + " ", it->second);
- for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it)
- dump_cell(f, indent + " ", it->second);
+ for (auto cell : module->cells())
+ dump_cell(f, indent + " ", cell);
for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
dump_process(f, indent + " ", it->second);
@@ -1995,16 +1992,16 @@ struct VerilogBackend : public Backend {
design->sort();
*f << stringf("/* Generated by %s */\n", yosys_version_str);
- for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
- if (it->second->get_blackbox_attribute() != blackboxes)
+ for (auto module : design->modules()) {
+ if (module->get_blackbox_attribute() != blackboxes)
continue;
- if (selected && !design->selected_whole_module(it->first)) {
- if (design->selected_module(it->first))
- log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(it->first));
+ if (selected && !design->selected_whole_module(module->name)) {
+ if (design->selected_module(module->name))
+ log_cmd_error("Can't handle partially selected module %s!\n", log_id(module->name));
continue;
}
- log("Dumping module `%s'.\n", it->first.c_str());
- dump_module(*f, "", it->second);
+ log("Dumping module `%s'.\n", module->name.c_str());
+ dump_module(*f, "", module);
}
auto_name_map.clear();
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 03:11:05 +0000