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-rw-r--r--backends/aiger/aiger.cc2
-rw-r--r--backends/aiger/xaiger.cc18
-rw-r--r--backends/btor/btor.cc5
-rw-r--r--backends/protobuf/protobuf.cc4
4 files changed, 16 insertions, 13 deletions
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index 0798fb35d..3e8b14dee 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -777,7 +777,7 @@ struct AigerBackend : public Backend {
}
break;
}
- extra_args(f, filename, args, argidx);
+ extra_args(f, filename, args, argidx, !ascii_mode);
Module *top_module = design->top_module();
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index fa6ba0aca..4018cc9de 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -350,6 +350,8 @@ struct XAigerWriter
if (!box_module || !box_module->attributes.count("\\abc_box_id"))
continue;
+ bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
+
// Fully pad all unused input connections of this box cell with S0
// Fully pad all undriven output connections of this box cell with anonymous wires
// NB: Assume box_module->ports are sorted alphabetically
@@ -394,7 +396,10 @@ struct XAigerWriter
rhs = it->second;
}
else {
- rhs = module->addWire(NEW_ID, GetSize(w));
+ Wire *wire = module->addWire(NEW_ID, GetSize(w));
+ if (blackbox)
+ wire->set_bool_attribute(ID(abc_padding));
+ rhs = wire;
cell->setPort(port_name, rhs);
}
@@ -405,12 +410,7 @@ struct XAigerWriter
if (O != b)
alias_map[O] = b;
undriven_bits.erase(O);
-
- auto jt = input_bits.find(b);
- if (jt != input_bits.end()) {
- log_assert(keep_bits.count(O));
- input_bits.erase(b);
- }
+ input_bits.erase(b);
}
}
}
@@ -429,7 +429,7 @@ struct XAigerWriter
// inherit existing inout's drivers
if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
|| keep_bits.count(bit)) {
- RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
+ RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());
RTLIL::Wire *new_wire = module->wire(wire_name);
if (!new_wire)
new_wire = module->addWire(wire_name, GetSize(wire));
@@ -856,7 +856,7 @@ struct XAigerBackend : public Backend {
}
break;
}
- extra_args(f, filename, args, argidx);
+ extra_args(f, filename, args, argidx, !ascii_mode);
Module *top_module = design->top_module();
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 4472993d4..f617b7ec2 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -897,9 +897,12 @@ struct BtorWorker
int sid = get_bv_sid(GetSize(s));
int nid = next_nid++;
- btorf("%d input %d %s\n", nid, sid);
+ btorf("%d input %d\n", nid, sid);
nid_width[nid] = GetSize(s);
+ for (int j = 0; j < GetSize(s); j++)
+ nidbits.push_back(make_pair(nid, j));
+
i += GetSize(s)-1;
continue;
}
diff --git a/backends/protobuf/protobuf.cc b/backends/protobuf/protobuf.cc
index fff110bb0..671686173 100644
--- a/backends/protobuf/protobuf.cc
+++ b/backends/protobuf/protobuf.cc
@@ -266,7 +266,7 @@ struct ProtobufBackend : public Backend {
}
break;
}
- extra_args(f, filename, args, argidx);
+ extra_args(f, filename, args, argidx, !text_mode);
log_header(design, "Executing Protobuf backend.\n");
@@ -338,7 +338,7 @@ struct ProtobufPass : public Pass {
if (!filename.empty()) {
rewrite_filename(filename);
std::ofstream *ff = new std::ofstream;
- ff->open(filename.c_str(), std::ofstream::trunc);
+ ff->open(filename.c_str(), text_mode ? std::ofstream::trunc : (std::ofstream::trunc | std::ofstream::binary));
if (ff->fail()) {
delete ff;
log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));