diff options
Diffstat (limited to 'examples/aiger')
| -rw-r--r-- | examples/aiger/demo.sh | 4 | ||||
| -rw-r--r-- | examples/aiger/demo.v | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/examples/aiger/demo.sh b/examples/aiger/demo.sh index caaa44761..8728b6722 100644 --- a/examples/aiger/demo.sh +++ b/examples/aiger/demo.sh @@ -4,11 +4,11 @@ yosys -p ' read_verilog -formal demo.v prep -flatten -nordff -top demo write_smt2 -wires demo.smt2 - miter -assert demo + flatten demo; delete -output memory_map; opt -full techmap; opt -fast abc -fast -g AND; opt_clean - write_aiger -miter -zinit -map demo.aim demo.aig + write_aiger -map demo.aim demo.aig ' super_prove demo.aig > demo.aiw yosys-smtbmc --dump-vcd demo.vcd --aig demo demo.smt2 diff --git a/examples/aiger/demo.v b/examples/aiger/demo.v index bb54ba4ef..b98287424 100644 --- a/examples/aiger/demo.v +++ b/examples/aiger/demo.v @@ -4,7 +4,7 @@ module demo(input clk, reset, ctrl); initial counter[NBITS-2] = 0; initial counter[0] = 1; always @(posedge clk) begin - counter <= reset ? 0 : ctrl ? counter + 1 : counter - 1; + counter <= reset ? 1 : ctrl ? counter + 1 : counter - 1; assume(counter != 0); assume(counter != 1 << (NBITS-1)); assert(counter != (1 << NBITS)-1); |