diff options
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/anlogic/.gitignore | 7 | ||||
| -rw-r--r-- | examples/anlogic/README | 12 | ||||
| -rwxr-xr-x | examples/anlogic/build.sh | 4 | ||||
| -rw-r--r-- | examples/anlogic/build.tcl | 11 | ||||
| -rw-r--r-- | examples/anlogic/demo.adc | 2 | ||||
| -rw-r--r-- | examples/anlogic/demo.v | 18 | ||||
| -rw-r--r-- | examples/anlogic/demo.ys | 3 | ||||
| -rw-r--r-- | examples/basys3/example.xdc | 3 | ||||
| -rw-r--r-- | examples/basys3/run_prog.tcl | 1 | ||||
| -rw-r--r-- | examples/cxx-api/evaldemo.cc | 2 | ||||
| -rw-r--r-- | examples/igloo2/.gitignore | 4 | ||||
| -rw-r--r-- | examples/igloo2/example.pdc | 20 | ||||
| -rw-r--r-- | examples/igloo2/example.sdc | 2 | ||||
| -rw-r--r-- | examples/igloo2/example.v | 64 | ||||
| -rw-r--r-- | examples/igloo2/libero.tcl | 57 | ||||
| -rw-r--r-- | examples/igloo2/runme.sh | 6 |
16 files changed, 215 insertions, 1 deletions
diff --git a/examples/anlogic/.gitignore b/examples/anlogic/.gitignore new file mode 100644 index 000000000..97c978a15 --- /dev/null +++ b/examples/anlogic/.gitignore @@ -0,0 +1,7 @@ +demo.bit +demo_phy.area +full.v +*.log +*.h +*.tde +*.svf diff --git a/examples/anlogic/README b/examples/anlogic/README new file mode 100644 index 000000000..35d8e9cb1 --- /dev/null +++ b/examples/anlogic/README @@ -0,0 +1,12 @@ +LED Blink project for Anlogic Lichee Tang board. + +Follow the install instructions for the Tang Dynasty IDE from given link below. + +https://tang.sipeed.com/en/getting-started/installing-td-ide/linux/ + + +set TD_HOME env variable to the full path to the TD <TD Install Directory> as follow. + +export TD_HOME=<TD Install Directory> + +then run "bash build.sh" in this directory. diff --git a/examples/anlogic/build.sh b/examples/anlogic/build.sh new file mode 100755 index 000000000..e0f6b4cfe --- /dev/null +++ b/examples/anlogic/build.sh @@ -0,0 +1,4 @@ +#!/bin/bash +set -ex +yosys demo.ys +$TD_HOME/bin/td build.tcl diff --git a/examples/anlogic/build.tcl b/examples/anlogic/build.tcl new file mode 100644 index 000000000..06db525c9 --- /dev/null +++ b/examples/anlogic/build.tcl @@ -0,0 +1,11 @@ +import_device eagle_s20.db -package BG256 +read_verilog full.v -top demo +read_adc demo.adc +optimize_rtl +map_macro +map +pack +place +route +report_area -io_info -file demo_phy.area +bitgen -bit demo.bit -version 0X0000 -svf demo.svf -svf_comment_on -g ucode:00000000000000000000000000000000 diff --git a/examples/anlogic/demo.adc b/examples/anlogic/demo.adc new file mode 100644 index 000000000..ec802502e --- /dev/null +++ b/examples/anlogic/demo.adc @@ -0,0 +1,2 @@ +set_pin_assignment {CLK_IN} { LOCATION = K14; } ##24MHZ +set_pin_assignment {R_LED} { LOCATION = R3; } ##R_LED diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v new file mode 100644 index 000000000..e17db771e --- /dev/null +++ b/examples/anlogic/demo.v @@ -0,0 +1,18 @@ +module demo ( + input wire CLK_IN, + output wire R_LED +); + parameter time1 = 30'd12_000_000; + reg led_state; + reg [29:0] count; + + always @(posedge CLK_IN)begin + if(count == time1)begin + count<= 30'd0; + led_state <= ~led_state; + end + else + count <= count + 1'b1; + end + assign R_LED = led_state; +endmodule diff --git a/examples/anlogic/demo.ys b/examples/anlogic/demo.ys new file mode 100644 index 000000000..cb396cc2b --- /dev/null +++ b/examples/anlogic/demo.ys @@ -0,0 +1,3 @@ +read_verilog demo.v +synth_anlogic -top demo +write_verilog full.v diff --git a/examples/basys3/example.xdc b/examples/basys3/example.xdc index c1fd0e925..8cdaa1996 100644 --- a/examples/basys3/example.xdc +++ b/examples/basys3/example.xdc @@ -19,3 +19,6 @@ set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1 } [get_ports {LD[15]}] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + diff --git a/examples/basys3/run_prog.tcl b/examples/basys3/run_prog.tcl index d711af840..b078ad511 100644 --- a/examples/basys3/run_prog.tcl +++ b/examples/basys3/run_prog.tcl @@ -1,3 +1,4 @@ +open_hw connect_hw_server open_hw_target [lindex [get_hw_targets] 0] set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0] diff --git a/examples/cxx-api/evaldemo.cc b/examples/cxx-api/evaldemo.cc index e5cc8d8e7..34373487d 100644 --- a/examples/cxx-api/evaldemo.cc +++ b/examples/cxx-api/evaldemo.cc @@ -22,7 +22,7 @@ struct EvalDemoPass : public Pass { EvalDemoPass() : Pass("evaldemo") { } - virtual void execute(vector<string>, Design *design) + void execute(vector<string>, Design *design) YS_OVERRIDE { Module *module = design->top_module(); diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore new file mode 100644 index 000000000..33b7182d3 --- /dev/null +++ b/examples/igloo2/.gitignore @@ -0,0 +1,4 @@ +/netlist.edn +/netlist.vm +/example.stp +/proj diff --git a/examples/igloo2/example.pdc b/examples/igloo2/example.pdc new file mode 100644 index 000000000..298d9e934 --- /dev/null +++ b/examples/igloo2/example.pdc @@ -0,0 +1,20 @@ +# Add placement constraints here + +set_io clk -pinname H16 -fixed yes -DIRECTION INPUT + +set_io SW1 -pinname H12 -fixed yes -DIRECTION INPUT +set_io SW2 -pinname H13 -fixed yes -DIRECTION INPUT + +set_io LED1 -pinname J16 -fixed yes -DIRECTION OUTPUT +set_io LED2 -pinname M16 -fixed yes -DIRECTION OUTPUT +set_io LED3 -pinname K16 -fixed yes -DIRECTION OUTPUT +set_io LED4 -pinname N16 -fixed yes -DIRECTION OUTPUT + +set_io AA -pinname L12 -fixed yes -DIRECTION OUTPUT +set_io AB -pinname L13 -fixed yes -DIRECTION OUTPUT +set_io AC -pinname M13 -fixed yes -DIRECTION OUTPUT +set_io AD -pinname N15 -fixed yes -DIRECTION OUTPUT +set_io AE -pinname L11 -fixed yes -DIRECTION OUTPUT +set_io AF -pinname L14 -fixed yes -DIRECTION OUTPUT +set_io AG -pinname N14 -fixed yes -DIRECTION OUTPUT +set_io CA -pinname M15 -fixed yes -DIRECTION OUTPUT diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc new file mode 100644 index 000000000..f8b487316 --- /dev/null +++ b/examples/igloo2/example.sdc @@ -0,0 +1,2 @@ +# Add timing constraints here +create_clock -period 10.000 -waveform {0.000 5.000} [get_ports {clk}] diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v new file mode 100644 index 000000000..4a9486e50 --- /dev/null +++ b/examples/igloo2/example.v @@ -0,0 +1,64 @@ +module example ( + input clk, + input SW1, + input SW2, + output LED1, + output LED2, + output LED3, + output LED4, + + output AA, AB, AC, AD, + output AE, AF, AG, CA +); + + localparam BITS = 8; + localparam LOG2DELAY = 22; + + reg [BITS+LOG2DELAY-1:0] counter = 0; + reg [BITS-1:0] outcnt; + + always @(posedge clk) begin + counter <= counter + SW1 + SW2 + 1; + outcnt <= counter >> LOG2DELAY; + end + + assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1); + + // assign CA = counter[10]; + // seg7enc seg7encinst ( + // .seg({AA, AB, AC, AD, AE, AF, AG}), + // .dat(CA ? outcnt[3:0] : outcnt[7:4]) + // ); + + assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[6:4]); + assign CA = outcnt[7]; +endmodule + +module seg7enc ( + input [3:0] dat, + output [6:0] seg +); + reg [6:0] seg_inv; + always @* begin + seg_inv = 0; + case (dat) + 4'h0: seg_inv = 7'b 0111111; + 4'h1: seg_inv = 7'b 0000110; + 4'h2: seg_inv = 7'b 1011011; + 4'h3: seg_inv = 7'b 1001111; + 4'h4: seg_inv = 7'b 1100110; + 4'h5: seg_inv = 7'b 1101101; + 4'h6: seg_inv = 7'b 1111101; + 4'h7: seg_inv = 7'b 0000111; + 4'h8: seg_inv = 7'b 1111111; + 4'h9: seg_inv = 7'b 1101111; + 4'hA: seg_inv = 7'b 1110111; + 4'hB: seg_inv = 7'b 1111100; + 4'hC: seg_inv = 7'b 0111001; + 4'hD: seg_inv = 7'b 1011110; + 4'hE: seg_inv = 7'b 1111001; + 4'hF: seg_inv = 7'b 1110001; + endcase + end + assign seg = ~seg_inv; +endmodule diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl new file mode 100644 index 000000000..abc94e479 --- /dev/null +++ b/examples/igloo2/libero.tcl @@ -0,0 +1,57 @@ +# Run with "libero SCRIPT:libero.tcl" + +file delete -force proj + +new_project \ + -name example \ + -location proj \ + -block_mode 0 \ + -hdl "VERILOG" \ + -family IGLOO2 \ + -die PA4MGL2500 \ + -package vf256 \ + -speed -1 + +import_files -hdl_source {netlist.vm} +import_files -sdc {example.sdc} +import_files -io_pdc {example.pdc} +build_design_hierarchy +set_option -synth 0 + +organize_tool_files -tool PLACEROUTE \ + -file {proj/constraint/example.sdc} \ + -file {proj/constraint/io/example.pdc} \ + -input_type constraint + +organize_tool_files -tool VERIFYTIMING \ + -file {proj/constraint/example.sdc} \ + -input_type constraint + +configure_tool -name PLACEROUTE \ + -params TDPR:true \ + -params PDPR:false \ + -params EFFORT_LEVEL:false \ + -params REPAIR_MIN_DELAY:false + +puts "" +puts "**> COMPILE" +run_tool -name {COMPILE} +puts "<** COMPILE" + +puts "" +puts "**> PLACEROUTE" +run_tool -name {PLACEROUTE} +puts "<** PLACEROUTE" + +puts "" +puts "**> VERIFYTIMING" +run_tool -name {VERIFYTIMING} +puts "<** VERIFYTIMING" + +puts "" +puts "**> BITSTREAM" +export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC} +puts "<** BITSTREAM" + +puts "" +exit 0 diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh new file mode 100644 index 000000000..a08894e0a --- /dev/null +++ b/examples/igloo2/runme.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -ex +yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v +export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost} +/opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl +cp proj/designer/example/export/example.stp . |