diff options
Diffstat (limited to 'frontends/aiger/aigerparse.cc')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 9c6096655..a72a82926 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -30,7 +30,7 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" -#include "kernel/consteval.h" +#include "kernel/celltypes.h" #include "aigerparse.h" YOSYS_NAMESPACE_BEGIN @@ -44,15 +44,11 @@ struct ConstEvalAig ConstEvalAig(RTLIL::Module *module) : module(module) { - CellTypes ct; - ct.setup_internals(); - ct.setup_stdcells(); - for (auto &it : module->cells_) { - if (!ct.cell_known(it.second->type)) + if (!yosys_celltypes.cell_known(it.second->type)) continue; for (auto &it2 : it.second->connections()) - if (ct.cell_output(it.second->type, it2.first)) { + if (yosys_celltypes.cell_output(it.second->type, it2.first)) { auto r = sig2driver.insert(std::make_pair(it2.second, it.second)); log_assert(r.second); } @@ -398,6 +394,7 @@ void AigerReader::parse_xaiger() log_assert(wire); input_sig.append(wire); } + // TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size()) ce.clear(); ce.compute_deps(output_sig, input_sig.to_sigbit_pool()); RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size()); |