diff options
Diffstat (limited to 'frontends/aiger/aigerparse.cc')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 33 |
1 files changed, 10 insertions, 23 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 4ecd01993..bd0596cc0 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -30,6 +30,7 @@ #include <libkern/OSByteOrder.h> #define __builtin_bswap32 OSSwapInt32 #endif +#define __STDC_FORMAT_MACROS #include <inttypes.h> #include "kernel/yosys.h" @@ -337,7 +338,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera return wire; } -void AigerReader::parse_xaiger() +void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup) { std::string header; f >> header; @@ -373,21 +374,6 @@ void AigerReader::parse_xaiger() if (n0) module->connect(n0, State::S0); - dict<int,IdString> box_lookup; - for (auto m : design->modules()) { - auto it = m->attributes.find("\\abc_box_id"); - if (it == m->attributes.end()) - continue; - if (m->name.begins_with("$paramod")) - continue; - auto id = it->second.as_int(); - auto r = box_lookup.insert(std::make_pair(id, m->name)); - if (!r.second) - log_error("Module '%s' has the same abc_box_id = %d value as '%s'.\n", - log_id(m), id, log_id(r.first->second)); - log_assert(r.second); - } - // Parse footer (symbol table, comments, etc.) std::string s; bool comment_seen = false; @@ -986,15 +972,16 @@ void AigerReader::post_process() } module->fixup_ports(); - design->add(module); - design->selection_stack.emplace_back(false); - RTLIL::Selection& sel = design->selection_stack.back(); - sel.select(module); + // Insert into a new (temporary) design so that "clean" will only + // operate (and run checks on) this one module + RTLIL::Design *mapped_design = new RTLIL::Design; + mapped_design->add(module); + Pass::call(mapped_design, "clean"); + mapped_design->modules_.erase(module->name); + delete mapped_design; - Pass::call(design, "clean"); - - design->selection_stack.pop_back(); + design->add(module); for (auto cell : module->cells().to_vector()) { if (cell->type != "$lut") continue; |