aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/ast/genrtlil.cc
diff options
context:
space:
mode:
Diffstat (limited to 'frontends/ast/genrtlil.cc')
-rw-r--r--frontends/ast/genrtlil.cc530
1 files changed, 269 insertions, 261 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 94f5c0a04..c0539252c 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -41,30 +41,28 @@ using namespace AST;
using namespace AST_INTERNAL;
// helper function for creating RTLIL code for unary operations
-static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
+static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
{
- std::stringstream sstr;
- sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
-
- RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
- cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
+ IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
+ RTLIL::Cell *cell = current_module->addCell(name, type);
+ cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
- wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
+ wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
if (gen_attributes)
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
- log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
+ log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
- cell->setPort("\\A", arg);
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed);
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(arg.size());
+ cell->setPort(ID::A, arg);
- cell->parameters["\\Y_WIDTH"] = result_width;
- cell->setPort("\\Y", wire);
+ cell->parameters[ID::Y_WIDTH] = result_width;
+ cell->setPort(ID::Y, wire);
return wire;
}
@@ -76,60 +74,56 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
return;
}
- std::stringstream sstr;
- sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
-
- RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
- cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
+ IdString name = stringf("$extend$%s:%d$%d", that->filename.c_str(), that->location.first_line, autoidx++);
+ RTLIL::Cell *cell = current_module->addCell(name, ID($pos));
+ cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
- wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
+ wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
if (that != NULL)
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
- log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
+ log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
- cell->setPort("\\A", sig);
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(is_signed);
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size());
+ cell->setPort(ID::A, sig);
- cell->parameters["\\Y_WIDTH"] = width;
- cell->setPort("\\Y", wire);
+ cell->parameters[ID::Y_WIDTH] = width;
+ cell->setPort(ID::Y, wire);
sig = wire;
}
// helper function for creating RTLIL code for binary operations
-static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
+static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
{
- std::stringstream sstr;
- sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
-
- RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
- cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
+ IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
+ RTLIL::Cell *cell = current_module->addCell(name, type);
+ cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
- wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
+ wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
- log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
+ log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
- cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed);
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed);
+ cell->parameters[ID::B_SIGNED] = RTLIL::Const(that->children[1]->is_signed);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
- cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(left.size());
+ cell->parameters[ID::B_WIDTH] = RTLIL::Const(right.size());
- cell->setPort("\\A", left);
- cell->setPort("\\B", right);
+ cell->setPort(ID::A, left);
+ cell->setPort(ID::B, right);
- cell->parameters["\\Y_WIDTH"] = result_width;
- cell->setPort("\\Y", wire);
+ cell->parameters[ID::Y_WIDTH] = result_width;
+ cell->setPort(ID::Y, wire);
return wire;
}
@@ -139,26 +133,26 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
log_assert(cond.size() == 1);
std::stringstream sstr;
- sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
+ sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
- RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
- cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
+ RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux));
+ cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
- wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
+ wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
- log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
+ log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
+ cell->parameters[ID::WIDTH] = RTLIL::Const(left.size());
- cell->setPort("\\A", right);
- cell->setPort("\\B", left);
- cell->setPort("\\S", cond);
- cell->setPort("\\Y", wire);
+ cell->setPort(ID::A, right);
+ cell->setPort(ID::B, left);
+ cell->setPort(ID::S, cond);
+ cell->setPort(ID::Y, wire);
return wire;
}
@@ -199,11 +193,11 @@ struct AST_INTERNAL::ProcessGenerator
{
// generate process and simple root case
proc = new RTLIL::Process;
- proc->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
- proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++);
+ proc->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
+ proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++);
for (auto &attr : always->attributes) {
if (attr.second->type != AST_CONSTANT)
- log_file_error(always->filename, always->linenum, "Attribute `%s' with non-constant value!\n",
+ log_file_error(always->filename, always->location.first_line, "Attribute `%s' with non-constant value!\n",
attr.first.c_str());
proc->attributes[attr.first] = attr.second->asAttrConst();
}
@@ -221,7 +215,7 @@ struct AST_INTERNAL::ProcessGenerator
for (auto child : always->children)
{
if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER &&
- child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) {
+ child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk)) {
found_global_syncs = true;
}
if (child->type == AST_EDGE) {
@@ -234,8 +228,8 @@ struct AST_INTERNAL::ProcessGenerator
if (found_anyedge_syncs) {
if (found_global_syncs)
- log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
- log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum);
+ log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n");
+ log("Note: Assuming pure combinatorial block at %s:%d.%d-%d.%d in\n", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
}
@@ -245,16 +239,16 @@ struct AST_INTERNAL::ProcessGenerator
for (auto child : always->children)
if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast &&
- child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk"))
+ child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk))
continue;
found_clocked_sync = true;
if (found_global_syncs || found_anyedge_syncs)
- log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
+ log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n");
RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
syncrule->signal = child->children[0]->genRTLIL();
if (GetSize(syncrule->signal) != 1)
- log_file_error(always->filename, always->linenum, "Found posedge/negedge event on a signal that is not 1 bit wide!\n");
+ log_file_error(always->filename, always->location.first_line, "Found posedge/negedge event on a signal that is not 1 bit wide!\n");
addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
proc->syncs.push_back(syncrule);
}
@@ -267,7 +261,7 @@ struct AST_INTERNAL::ProcessGenerator
}
// create initial assignments for the temporary signals
- if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
+ if ((flag_nolatches || always->get_bool_attribute(ID::nolatches) || current_module->get_bool_attribute(ID::nolatches)) && !found_clocked_sync) {
subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
} else {
addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
@@ -335,7 +329,7 @@ struct AST_INTERNAL::ProcessGenerator
} while (current_module->wires_.count(wire_name) > 0);
RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
- wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
+ wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
chunk.wire = wire;
chunk.offset = 0;
@@ -420,7 +414,7 @@ struct AST_INTERNAL::ProcessGenerator
for (auto &lvalue_c : lvalue.chunks()) {
RTLIL::SigSpec lhs = lvalue_c;
RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width);
- if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync"))
+ if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute(ID::nosync))
rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
remove_unwanted_lvalue_bits(lhs, rhs);
actions.push_back(RTLIL::SigSig(lhs, rhs));
@@ -470,13 +464,13 @@ struct AST_INTERNAL::ProcessGenerator
case AST_CASE:
{
RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
- sw->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
+ sw->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
current_case->switches.push_back(sw);
for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT)
- log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
+ log_file_error(ast->filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
sw->attributes[attr.first] = attr.second->asAttrConst();
}
@@ -504,7 +498,7 @@ struct AST_INTERNAL::ProcessGenerator
RTLIL::CaseRule *backup_case = current_case;
current_case = new RTLIL::CaseRule;
- current_case->attributes["\\src"] = stringf("%s:%d", child->filename.c_str(), child->linenum);
+ current_case->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column);
last_generated_case = current_case;
addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
for (auto node : child->children) {
@@ -525,7 +519,7 @@ struct AST_INTERNAL::ProcessGenerator
subst_rvalue_map.restore();
}
- if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
+ if (last_generated_case != NULL && ast->get_bool_attribute(ID::full_case) && default_case == NULL) {
#if 0
// this is a valid transformation, but as optimization it is premature.
// better: add a default case that assigns 'x' to everything, and let later
@@ -554,16 +548,16 @@ struct AST_INTERNAL::ProcessGenerator
break;
case AST_WIRE:
- log_file_error(ast->filename, ast->linenum, "Found reg declaration in block without label!\n");
+ log_file_error(ast->filename, ast->location.first_line, "Found reg declaration in block without label!\n");
break;
case AST_ASSIGN:
- log_file_error(ast->filename, ast->linenum, "Found continous assignment in always/initial block!\n");
+ log_file_error(ast->filename, ast->location.first_line, "Found continous assignment in always/initial block!\n");
break;
case AST_PARAMETER:
case AST_LOCALPARAM:
- log_file_error(ast->filename, ast->linenum, "Found parameter declaration in block without label!\n");
+ log_file_error(ast->filename, ast->location.first_line, "Found parameter declaration in block without label!\n");
break;
case AST_NONE:
@@ -595,6 +589,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
switch (type)
{
+ case AST_NONE:
+ // unallocated enum, ignore
+ break;
case AST_CONSTANT:
width_hint = max(width_hint, int(bits.size()));
if (!is_signed)
@@ -611,8 +608,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (id_ast == NULL && current_scope.count(str))
id_ast = current_scope.at(str);
if (!id_ast)
- log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", str.c_str());
- if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM) {
+ log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", str.c_str());
+ if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) {
if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
} else
@@ -621,7 +618,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (id_ast->children[0]->type == AST_CONSTANT)
this_width = id_ast->children[0]->bits.size();
else
- log_file_error(filename, linenum, "Failed to detect width for parameter %s!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Failed to detect width for parameter %s!\n", str.c_str());
if (children.size() != 0)
range = children[0];
} else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) {
@@ -633,7 +630,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
// log("---\n");
// id_ast->dumpAst(NULL, "decl> ");
// dumpAst(NULL, "ref> ");
- log_file_error(filename, linenum, "Failed to detect width of signal access `%s'!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Failed to detect width of signal access `%s'!\n", str.c_str());
}
} else {
this_width = id_ast->range_left - id_ast->range_right + 1;
@@ -644,12 +641,12 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
this_width = 32;
} else if (id_ast->type == AST_MEMORY) {
if (!id_ast->children[0]->range_valid)
- log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", str.c_str());
this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
if (children.size() > 1)
range = children[1];
} else
- log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Failed to detect width for identifier %s!\n", str.c_str());
if (range) {
if (range->children.size() == 1)
this_width = 1;
@@ -659,7 +656,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
delete left_at_zero_ast;
delete right_at_zero_ast;
@@ -675,7 +672,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
case AST_TO_BITS:
while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { }
if (children[0]->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Left operand of tobits expression is not constant!\n");
+ log_file_error(filename, location.first_line, "Left operand of tobits expression is not constant!\n");
children[1]->detectSignWidthWorker(sub_width_hint, sign_hint);
width_hint = max(width_hint, children[0]->bitsAsConst().as_int());
break;
@@ -703,7 +700,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
case AST_REPLICATE:
while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
if (children[0]->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
+ log_file_error(filename, location.first_line, "Left operand of replicate expression is not constant!\n");
children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
sign_hint = false;
@@ -777,7 +774,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (!id2ast->is_signed)
sign_hint = false;
if (!id2ast->children[0]->range_valid)
- log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", str.c_str());
this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
width_hint = max(width_hint, this_width);
break;
@@ -787,7 +784,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (GetSize(children) == 1) {
while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
if (children[0]->type != AST_CONSTANT)
- log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
+ log_file_error(filename, location.first_line, "System function %s called with non-const argument!\n",
RTLIL::unescape_id(str).c_str());
width_hint = max(width_hint, int(children[0]->asInt(true)));
}
@@ -809,7 +806,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
default:
for (auto f : log_files)
current_ast_mod->dumpAst(f, "verilog-ast> ");
- log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
+ log_file_error(filename, location.first_line, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
}
if (*found_real)
@@ -839,10 +836,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
// cases this variable is used to hold the type of the cell that should
// be instantiated for this type of AST node.
- std::string type_name;
+ IdString type_name;
current_filename = filename;
- set_line_num(linenum);
switch (type)
{
@@ -861,6 +857,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_GENIF:
case AST_GENCASE:
case AST_PACKAGE:
+ case AST_ENUM:
case AST_MODPORT:
case AST_MODPORTMEMBER:
case AST_TYPEDEF:
@@ -870,19 +867,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// This is used by the hierarchy pass to know when it can replace interface connection with the individual
// signals.
RTLIL::Wire *wire = current_module->addWire(str, 1);
- wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+ wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
wire->start_offset = 0;
wire->port_id = port_id;
wire->port_input = true;
wire->port_output = true;
- wire->set_bool_attribute("\\is_interface");
+ wire->set_bool_attribute(ID::is_interface);
if (children.size() > 0) {
for(size_t i=0; i<children.size();i++) {
if(children[i]->type == AST_INTERFACEPORTTYPE) {
std::pair<std::string,std::string> res = AST::split_modport_from_type(children[i]->str);
- wire->attributes["\\interface_type"] = res.first;
+ wire->attributes[ID::interface_type] = res.first;
if (res.second != "")
- wire->attributes["\\interface_modport"] = res.second;
+ wire->attributes[ID::interface_modport] = res.second;
break;
}
}
@@ -901,18 +898,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (flag_pwires)
{
if (GetSize(children) < 1 || children[0]->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Parameter `%s' with non-constant value!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Parameter `%s' with non-constant value!\n", str.c_str());
RTLIL::Const val = children[0]->bitsAsConst();
RTLIL::Wire *wire = current_module->addWire(str, GetSize(val));
current_module->connect(wire, val);
- wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
- wire->attributes[type == AST_PARAMETER ? "\\parameter" : "\\localparam"] = 1;
+ wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+ wire->attributes[type == AST_PARAMETER ? ID::parameter : ID::localparam] = 1;
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
+ log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
wire->attributes[attr.first] = attr.second->asAttrConst();
}
}
@@ -921,15 +918,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// create an RTLIL::Wire for an AST_WIRE node
case AST_WIRE: {
if (current_module->wires_.count(str) != 0)
- log_file_error(filename, linenum, "Re-definition of signal `%s'!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Re-definition of signal `%s'!\n", str.c_str());
if (!range_valid)
- log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Signal `%s' with non-constant width!\n", str.c_str());
if (!(range_left >= range_right || (range_left == -1 && range_right == 0)))
- log_file_error(filename, linenum, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
+ log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
- wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+ wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
wire->start_offset = range_right;
wire->port_id = port_id;
wire->port_input = is_input;
@@ -938,29 +935,29 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
+ log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
wire->attributes[attr.first] = attr.second->asAttrConst();
}
- if (is_wand) wire->set_bool_attribute("\\wand");
- if (is_wor) wire->set_bool_attribute("\\wor");
+ if (is_wand) wire->set_bool_attribute(ID::wand);
+ if (is_wor) wire->set_bool_attribute(ID::wor);
}
break;
// create an RTLIL::Memory for an AST_MEMORY node
case AST_MEMORY: {
if (current_module->memories.count(str) != 0)
- log_file_error(filename, linenum, "Re-definition of memory `%s'!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Re-definition of memory `%s'!\n", str.c_str());
log_assert(children.size() >= 2);
log_assert(children[0]->type == AST_RANGE);
log_assert(children[1]->type == AST_RANGE);
if (!children[0]->range_valid || !children[1]->range_valid)
- log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str());
RTLIL::Memory *memory = new RTLIL::Memory;
- memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+ memory->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
memory->name = str;
memory->width = children[0]->range_left - children[0]->range_right + 1;
if (children[1]->range_right < children[1]->range_left) {
@@ -974,7 +971,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
+ log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
memory->attributes[attr.first] = attr.second->asAttrConst();
}
}
@@ -997,7 +994,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
RTLIL::SigSpec sig = realAsConst(width_hint);
- log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
+ log_file_warning(filename, location.first_line, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
return sig;
}
@@ -1015,22 +1012,22 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
RTLIL::Wire *wire = current_module->addWire(str);
- wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+ wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
wire->name = str;
if (flag_autowire)
- log_file_warning(filename, linenum, "Identifier `%s' is implicitly declared.\n", str.c_str());
+ log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str());
else
- log_file_error(filename, linenum, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
+ log_file_error(filename, location.first_line, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
}
- else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
+ else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM || id2ast->type == AST_ENUM_ITEM) {
if (id2ast->children[0]->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Parameter %s does not evaluate to constant value!\n", str.c_str());
chunk = RTLIL::Const(id2ast->children[0]->bits);
goto use_const_chunk;
}
else if (id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) {
RTLIL::Wire *current_wire = current_module->wire(str);
- if (current_wire->get_bool_attribute("\\is_interface"))
+ if (current_wire->get_bool_attribute(ID::is_interface))
is_interface = true;
// Ignore
}
@@ -1039,26 +1036,23 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
is_interface = true;
}
else {
- log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Identifier `%s' doesn't map to any signal!\n", str.c_str());
}
if (id2ast->type == AST_MEMORY)
- log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Identifier `%s' does map to an unexpanded memory!\n", str.c_str());
// If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface'
// This makes it possible for the hierarchy pass to see what are interface connections and then replace them
// with the individual signals:
if (is_interface) {
- RTLIL::Wire *dummy_wire;
- std::string dummy_wire_name = "$dummywireforinterface" + str;
- if (current_module->wires_.count(dummy_wire_name))
- dummy_wire = current_module->wires_[dummy_wire_name];
- else {
+ IdString dummy_wire_name = stringf("$dummywireforinterface%s", str.c_str());
+ RTLIL::Wire *dummy_wire = current_module->wire(dummy_wire_name);
+ if (!dummy_wire) {
dummy_wire = current_module->addWire(dummy_wire_name);
- dummy_wire->set_bool_attribute("\\is_interface");
+ dummy_wire->set_bool_attribute(ID::is_interface);
}
- RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire);
- return tmp;
+ return dummy_wire;
}
wire = current_module->wires_[str];
@@ -1069,7 +1063,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
use_const_chunk:
if (children.size() != 0) {
if (children[0]->type != AST_RANGE)
- log_file_error(filename, linenum, "Single range expected.\n");
+ log_file_error(filename, location.first_line, "Single range expected.\n");
int source_width = id2ast->range_left - id2ast->range_right + 1;
int source_offset = id2ast->range_right;
if (!children[0]->range_valid) {
@@ -1078,7 +1072,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
children[0]->children[1]->clone() : children[0]->children[0]->clone());
@@ -1094,7 +1088,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
if (GetSize(shift_val) >= 32)
fake_ast->children[1]->is_signed = true;
- RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val);
+ RTLIL::SigSpec sig = binop2rtlil(fake_ast, ID($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val);
delete left_at_zero_ast;
delete right_at_zero_ast;
delete fake_ast;
@@ -1106,10 +1100,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
if (chunk.width == 1)
- log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
+ log_file_warning(filename, location.first_line, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
str.c_str());
else
- log_file_warning(filename, linenum, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
+ log_file_warning(filename, location.first_line, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width);
chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
} else {
@@ -1123,10 +1117,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
chunk.offset += add_undef_bits_lsb;
}
if (add_undef_bits_lsb)
- log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
+ log_file_warning(filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb);
if (add_undef_bits_msb)
- log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
+ log_file_warning(filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb);
}
}
@@ -1166,7 +1160,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::SigSpec left = children[0]->genRTLIL();
RTLIL::SigSpec right = children[1]->genRTLIL();
if (!left.is_fully_const())
- log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
+ log_file_error(filename, location.first_line, "Left operand of replicate expression is not constant!\n");
int count = left.as_int();
RTLIL::SigSpec sig;
for (int i = 0; i < count; i++)
@@ -1178,9 +1172,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
// generate cells for unary operations: $not, $pos, $neg
- if (0) { case AST_BIT_NOT: type_name = "$not"; }
- if (0) { case AST_POS: type_name = "$pos"; }
- if (0) { case AST_NEG: type_name = "$neg"; }
+ if (0) { case AST_BIT_NOT: type_name = ID($not); }
+ if (0) { case AST_POS: type_name = ID($pos); }
+ if (0) { case AST_NEG: type_name = ID($neg); }
{
RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
is_signed = children[0]->is_signed;
@@ -1193,10 +1187,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
// generate cells for binary operations: $and, $or, $xor, $xnor
- if (0) { case AST_BIT_AND: type_name = "$and"; }
- if (0) { case AST_BIT_OR: type_name = "$or"; }
- if (0) { case AST_BIT_XOR: type_name = "$xor"; }
- if (0) { case AST_BIT_XNOR: type_name = "$xnor"; }
+ if (0) { case AST_BIT_AND: type_name = ID($and); }
+ if (0) { case AST_BIT_OR: type_name = ID($or); }
+ if (0) { case AST_BIT_XOR: type_name = ID($xor); }
+ if (0) { case AST_BIT_XNOR: type_name = ID($xnor); }
{
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
@@ -1210,10 +1204,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
// generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
- if (0) { case AST_REDUCE_AND: type_name = "$reduce_and"; }
- if (0) { case AST_REDUCE_OR: type_name = "$reduce_or"; }
- if (0) { case AST_REDUCE_XOR: type_name = "$reduce_xor"; }
- if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; }
+ if (0) { case AST_REDUCE_AND: type_name = ID($reduce_and); }
+ if (0) { case AST_REDUCE_OR: type_name = ID($reduce_or); }
+ if (0) { case AST_REDUCE_XOR: type_name = ID($reduce_xor); }
+ if (0) { case AST_REDUCE_XNOR: type_name = ID($reduce_xnor); }
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg);
@@ -1222,7 +1216,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// generate cells for unary operations: $reduce_bool
// (this is actually just an $reduce_or, but for clarity a different cell type is used)
- if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
+ if (0) { case AST_REDUCE_BOOL: type_name = ID($reduce_bool); }
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg;
@@ -1230,10 +1224,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
// generate cells for binary operations: $shl, $shr, $sshl, $sshr
- if (0) { case AST_SHIFT_LEFT: type_name = "$shl"; }
- if (0) { case AST_SHIFT_RIGHT: type_name = "$shr"; }
- if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; }
- if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; }
+ if (0) { case AST_SHIFT_LEFT: type_name = ID($shl); }
+ if (0) { case AST_SHIFT_RIGHT: type_name = ID($shr); }
+ if (0) { case AST_SHIFT_SLEFT: type_name = ID($sshl); }
+ if (0) { case AST_SHIFT_SRIGHT: type_name = ID($sshr); }
{
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
@@ -1257,19 +1251,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int width = width_hint > 0 ? width_hint : left.size();
is_signed = children[0]->is_signed;
if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
- return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.size()), right);
- return binop2rtlil(this, "$pow", width, left, right);
+ return binop2rtlil(this, ID($shl), width, RTLIL::SigSpec(1, left.size()), right);
+ return binop2rtlil(this, ID($pow), width, left, right);
}
// generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
- if (0) { case AST_LT: type_name = "$lt"; }
- if (0) { case AST_LE: type_name = "$le"; }
- if (0) { case AST_EQ: type_name = "$eq"; }
- if (0) { case AST_NE: type_name = "$ne"; }
- if (0) { case AST_EQX: type_name = "$eqx"; }
- if (0) { case AST_NEX: type_name = "$nex"; }
- if (0) { case AST_GE: type_name = "$ge"; }
- if (0) { case AST_GT: type_name = "$gt"; }
+ if (0) { case AST_LT: type_name = ID($lt); }
+ if (0) { case AST_LE: type_name = ID($le); }
+ if (0) { case AST_EQ: type_name = ID($eq); }
+ if (0) { case AST_NE: type_name = ID($ne); }
+ if (0) { case AST_EQX: type_name = ID($eqx); }
+ if (0) { case AST_NEX: type_name = ID($nex); }
+ if (0) { case AST_GE: type_name = ID($ge); }
+ if (0) { case AST_GT: type_name = ID($gt); }
{
int width = max(width_hint, 1);
width_hint = -1, sign_hint = true;
@@ -1282,11 +1276,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
// generate cells for binary operations: $add, $sub, $mul, $div, $mod
- if (0) { case AST_ADD: type_name = "$add"; }
- if (0) { case AST_SUB: type_name = "$sub"; }
- if (0) { case AST_MUL: type_name = "$mul"; }
- if (0) { case AST_DIV: type_name = "$div"; }
- if (0) { case AST_MOD: type_name = "$mod"; }
+ if (0) { case AST_ADD: type_name = ID($add); }
+ if (0) { case AST_SUB: type_name = ID($sub); }
+ if (0) { case AST_MUL: type_name = ID($mul); }
+ if (0) { case AST_DIV: type_name = ID($div); }
+ if (0) { case AST_MOD: type_name = ID($mod); }
{
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
@@ -1312,8 +1306,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
// generate cells for binary operations: $logic_and, $logic_or
- if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; }
- if (0) { case AST_LOGIC_OR: type_name = "$logic_or"; }
+ if (0) { case AST_LOGIC_AND: type_name = ID($logic_and); }
+ if (0) { case AST_LOGIC_OR: type_name = ID($logic_or); }
{
RTLIL::SigSpec left = children[0]->genRTLIL();
RTLIL::SigSpec right = children[1]->genRTLIL();
@@ -1324,7 +1318,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_LOGIC_NOT:
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
- return uniop2rtlil(this, "$logic_not", max(width_hint, 1), arg);
+ return uniop2rtlil(this, ID($logic_not), max(width_hint, 1), arg);
}
// generate multiplexer for ternary operator (aka ?:-operator)
@@ -1334,18 +1328,31 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
detectSignWidth(width_hint, sign_hint);
RTLIL::SigSpec cond = children[0]->genRTLIL();
- RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
- RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
+ RTLIL::SigSpec sig;
+ if (cond.is_fully_const()) {
+ if (cond.as_bool()) {
+ sig = children[1]->genRTLIL(width_hint, sign_hint);
+ widthExtend(this, sig, sig.size(), children[1]->is_signed);
+ }
+ else {
+ sig = children[2]->genRTLIL(width_hint, sign_hint);
+ widthExtend(this, sig, sig.size(), children[2]->is_signed);
+ }
+ }
+ else {
+ RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
+ RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
- if (cond.size() > 1)
- cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
+ if (cond.size() > 1)
+ cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false);
- int width = max(val1.size(), val2.size());
- is_signed = children[1]->is_signed && children[2]->is_signed;
- widthExtend(this, val1, width, is_signed);
- widthExtend(this, val2, width, is_signed);
+ int width = max(val1.size(), val2.size());
+ is_signed = children[1]->is_signed && children[2]->is_signed;
+ widthExtend(this, val1, width, is_signed);
+ widthExtend(this, val2, width, is_signed);
- RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);
+ sig = mux2rtlil(this, cond, val1, val2);
+ }
if (sig.size() < width_hint)
sig.extend_u0(width_hint, sign_hint);
@@ -1356,13 +1363,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_MEMRD:
{
std::stringstream sstr;
- sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
+ sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
- RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
- cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+ RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd));
+ cell->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
- wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+ wire->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line);
int mem_width, mem_size, addr_bits;
is_signed = id2ast->is_signed;
@@ -1370,18 +1377,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
- cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
- cell->setPort("\\EN", RTLIL::SigSpec(RTLIL::State::Sx, 1));
- cell->setPort("\\ADDR", addr_sig);
- cell->setPort("\\DATA", RTLIL::SigSpec(wire));
+ cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1));
+ cell->setPort(ID::EN, RTLIL::SigSpec(RTLIL::State::Sx, 1));
+ cell->setPort(ID::ADDR, addr_sig);
+ cell->setPort(ID::DATA, RTLIL::SigSpec(wire));
- cell->parameters["\\MEMID"] = RTLIL::Const(str);
- cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
- cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width);
+ cell->parameters[ID::MEMID] = RTLIL::Const(str);
+ cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
+ cell->parameters[ID::WIDTH] = RTLIL::Const(wire->width);
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
- cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(0);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(0);
+ cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0);
if (!sign_hint)
is_signed = false;
@@ -1394,10 +1401,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_MEMINIT:
{
std::stringstream sstr;
- sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
+ sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
- RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit");
- cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+ RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? ID($memwr) : ID($meminit));
+ cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
int mem_width, mem_size, addr_bits;
id2ast->meminfo(mem_width, mem_size, addr_bits);
@@ -1405,28 +1412,28 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int num_words = 1;
if (type == AST_MEMINIT) {
if (children[2]->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Memory init with non-constant word count!\n");
+ log_file_error(filename, location.first_line, "Memory init with non-constant word count!\n");
num_words = int(children[2]->asInt(false));
- cell->parameters["\\WORDS"] = RTLIL::Const(num_words);
+ cell->parameters[ID::WORDS] = RTLIL::Const(num_words);
}
SigSpec addr_sig = children[0]->genRTLIL();
- cell->setPort("\\ADDR", addr_sig);
- cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words));
+ cell->setPort(ID::ADDR, addr_sig);
+ cell->setPort(ID::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words));
- cell->parameters["\\MEMID"] = RTLIL::Const(str);
- cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
- cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);
+ cell->parameters[ID::MEMID] = RTLIL::Const(str);
+ cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
+ cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[str]->width);
if (type == AST_MEMWR) {
- cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
- cell->setPort("\\EN", children[2]->genRTLIL());
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
+ cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1));
+ cell->setPort(ID::EN, children[2]->genRTLIL());
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(0);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(0);
}
- cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1);
+ cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
}
break;
@@ -1437,12 +1444,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_FAIR:
case AST_COVER:
{
- const char *celltype = nullptr;
- if (type == AST_ASSERT) celltype = "$assert";
- if (type == AST_ASSUME) celltype = "$assume";
- if (type == AST_LIVE) celltype = "$live";
- if (type == AST_FAIR) celltype = "$fair";
- if (type == AST_COVER) celltype = "$cover";
+ IdString celltype;
+ if (type == AST_ASSERT) celltype = ID($assert);
+ if (type == AST_ASSUME) celltype = ID($assume);
+ if (type == AST_LIVE) celltype = ID($live);
+ if (type == AST_FAIR) celltype = ID($fair);
+ if (type == AST_COVER) celltype = ID($cover);
log_assert(children.size() == 2);
@@ -1455,25 +1462,22 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
en = current_module->ReduceBool(NEW_ID, en);
IdString cellname;
- if (str.empty()) {
- std::stringstream sstr;
- sstr << celltype << "$" << filename << ":" << linenum << "$" << (autoidx++);
- cellname = sstr.str();
- } else {
+ if (str.empty())
+ cellname = stringf("%s$%s:%d$%d", celltype.c_str(), filename.c_str(), location.first_line, autoidx++);
+ else
cellname = str;
- }
RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
- cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+ cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
+ log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- cell->setPort("\\A", check);
- cell->setPort("\\EN", en);
+ cell->setPort(ID::A, check);
+ cell->setPort(ID::EN, en);
}
break;
@@ -1489,7 +1493,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
new_left.append(left[i]);
new_right.append(right[i]);
}
- log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n"
+ log_file_warning(filename, location.first_line, "Ignoring assignment to constant bits:\n"
" old assignment: %s = %s\n new assignment: %s = %s.\n",
log_signal(left), log_signal(right),
log_signal(new_left), log_signal(new_right));
@@ -1506,12 +1510,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int port_counter = 0, para_counter = 0;
if (current_module->count_id(str) != 0)
- log_file_error(filename, linenum, "Re-definition of cell `%s'!\n", str.c_str());
+ log_file_error(filename, location.first_line, "Re-definition of cell `%s'!\n", str.c_str());
RTLIL::Cell *cell = current_module->addCell(str, "");
- cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+ cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
- cell->set_bool_attribute("\\module_not_derived");
+ cell->set_bool_attribute(ID::module_not_derived);
for (auto it = children.begin(); it != children.end(); it++) {
AstNode *child = *it;
@@ -1525,7 +1529,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int extra_const_flags = 0;
IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
if (child->children[0]->type == AST_REALVALUE) {
- log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n",
+ log_file_warning(filename, location.first_line, "Replacing floating point parameter %s.%s = %f with string.\n",
log_id(cell), log_id(paraname), child->children[0]->realvalue);
extra_const_flags = RTLIL::CONST_FLAG_REAL;
auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue));
@@ -1533,7 +1537,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
delete strnode;
}
if (child->children[0]->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n",
+ log_file_error(filename, location.first_line, "Parameter %s.%s with non-constant value!\n",
log_id(cell), log_id(paraname));
cell->parameters[paraname] = child->children[0]->asParaConst();
cell->parameters[paraname].flags |= extra_const_flags;
@@ -1556,28 +1560,32 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
+ log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- if (cell->type.in("$specify2", "$specify3")) {
- int src_width = GetSize(cell->getPort("\\SRC"));
- int dst_width = GetSize(cell->getPort("\\DST"));
- bool full = cell->getParam("\\FULL").as_bool();
+ if (cell->type == ID($specify2)) {
+ int src_width = GetSize(cell->getPort(ID::SRC));
+ int dst_width = GetSize(cell->getPort(ID::DST));
+ bool full = cell->getParam(ID::FULL).as_bool();
if (!full && src_width != dst_width)
- log_file_error(filename, linenum, "Parallel specify SRC width does not match DST width.\n");
- if (cell->type == "$specify3") {
- int dat_width = GetSize(cell->getPort("\\DAT"));
- if (dat_width != dst_width)
- log_file_error(filename, linenum, "Specify DAT width does not match DST width.\n");
- }
- cell->setParam("\\SRC_WIDTH", Const(src_width));
- cell->setParam("\\DST_WIDTH", Const(dst_width));
+ log_file_error(filename, location.first_line, "Parallel specify SRC width does not match DST width.\n");
+ cell->setParam(ID::SRC_WIDTH, Const(src_width));
+ cell->setParam(ID::DST_WIDTH, Const(dst_width));
+ }
+ else if (cell->type == ID($specify3)) {
+ int dat_width = GetSize(cell->getPort(ID::DAT));
+ int dst_width = GetSize(cell->getPort(ID::DST));
+ if (dat_width != dst_width)
+ log_file_error(filename, location.first_line, "Specify DAT width does not match DST width.\n");
+ int src_width = GetSize(cell->getPort(ID::SRC));
+ cell->setParam(ID::SRC_WIDTH, Const(src_width));
+ cell->setParam(ID::DST_WIDTH, Const(dst_width));
}
- if (cell->type == "$specrule") {
- int src_width = GetSize(cell->getPort("\\SRC"));
- int dst_width = GetSize(cell->getPort("\\DST"));
- cell->setParam("\\SRC_WIDTH", Const(src_width));
- cell->setParam("\\DST_WIDTH", Const(dst_width));
+ else if (cell->type == ID($specrule)) {
+ int src_width = GetSize(cell->getPort(ID::SRC));
+ int dst_width = GetSize(cell->getPort(ID::DST));
+ cell->setParam(ID::SRC_WIDTH, Const(src_width));
+ cell->setParam(ID::DST_WIDTH, Const(dst_width));
}
}
break;
@@ -1600,30 +1608,30 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int sz = children.size();
if (str == "$info") {
if (sz > 0)
- log_file_info(filename, linenum, "%s.\n", children[0]->str.c_str());
+ log_file_info(filename, location.first_line, "%s.\n", children[0]->str.c_str());
else
- log_file_info(filename, linenum, "\n");
+ log_file_info(filename, location.first_line, "\n");
} else if (str == "$warning") {
if (sz > 0)
- log_file_warning(filename, linenum, "%s.\n", children[0]->str.c_str());
+ log_file_warning(filename, location.first_line, "%s.\n", children[0]->str.c_str());
else
- log_file_warning(filename, linenum, "\n");
+ log_file_warning(filename, location.first_line, "\n");
} else if (str == "$error") {
if (sz > 0)
- log_file_error(filename, linenum, "%s.\n", children[0]->str.c_str());
+ log_file_error(filename, location.first_line, "%s.\n", children[0]->str.c_str());
else
- log_file_error(filename, linenum, "\n");
+ log_file_error(filename, location.first_line, "\n");
} else if (str == "$fatal") {
// TODO: 1st parameter, if exists, is 0,1 or 2, and passed to $finish()
// if no parameter is given, default value is 1
// dollar_finish(sz ? children[0] : 1);
// perhaps create & use log_file_fatal()
if (sz > 0)
- log_file_error(filename, linenum, "FATAL: %s.\n", children[0]->str.c_str());
+ log_file_error(filename, location.first_line, "FATAL: %s.\n", children[0]->str.c_str());
else
- log_file_error(filename, linenum, "FATAL.\n");
+ log_file_error(filename, location.first_line, "FATAL.\n");
} else {
- log_file_error(filename, linenum, "Unknown elabortoon system task '%s'.\n", str.c_str());
+ log_file_error(filename, location.first_line, "Unknown elabortoon system task '%s'.\n", str.c_str());
}
} break;
@@ -1634,33 +1642,33 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int width = width_hint;
if (GetSize(children) > 1)
- log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 0.\n",
+ log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1 or 0.\n",
RTLIL::unescape_id(str).c_str(), GetSize(children));
if (GetSize(children) == 1) {
if (children[0]->type != AST_CONSTANT)
- log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
+ log_file_error(filename, location.first_line, "System function %s called with non-const argument!\n",
RTLIL::unescape_id(str).c_str());
width = children[0]->asInt(true);
}
if (width <= 0)
- log_file_error(filename, linenum, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
+ log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
Cell *cell = current_module->addCell(myid, str.substr(1));
- cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
- cell->parameters["\\WIDTH"] = width;
+ cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+ cell->parameters[ID::WIDTH] = width;
- if (attributes.count("\\reg")) {
- auto &attr = attributes.at("\\reg");
+ if (attributes.count(ID::reg)) {
+ auto &attr = attributes.at(ID::reg);
if (attr->type != AST_CONSTANT)
- log_file_error(filename, linenum, "Attribute `reg' with non-constant value!\n");
- cell->attributes["\\reg"] = attr->asAttrConst();
+ log_file_error(filename, location.first_line, "Attribute `reg' with non-constant value!\n");
+ cell->attributes[ID::reg] = attr->asAttrConst();
}
Wire *wire = current_module->addWire(myid + "_wire", width);
- wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
- cell->setPort("\\Y", wire);
+ wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+ cell->setPort(ID::Y, wire);
is_signed = sign_hint;
return SigSpec(wire);
@@ -1672,7 +1680,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto f : log_files)
current_ast_mod->dumpAst(f, "verilog-ast> ");
type_name = type2str(type);
- log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str());
+ log_file_error(filename, location.first_line, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str());
}
return RTLIL::SigSpec();
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-24 19:02:41 +0000