diff options
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/ast.cc | 278 | ||||
| -rw-r--r-- | frontends/ast/ast.h | 24 | ||||
| -rw-r--r-- | frontends/ast/genrtlil.cc | 530 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 683 |
4 files changed, 882 insertions, 633 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 5bbea0faf..2b6002548 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -88,6 +88,8 @@ std::string AST::type2str(AstNodeType type) X(AST_LIVE) X(AST_FAIR) X(AST_COVER) + X(AST_ENUM) + X(AST_ENUM_ITEM) X(AST_FCALL) X(AST_TO_BITS) X(AST_TO_SIGNED) @@ -180,7 +182,7 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id) AstNode *attr = attributes.at(id); if (attr->type != AST_CONSTANT) - log_file_error(attr->filename, attr->linenum, "Attribute `%s' with non-constant value!\n", id.c_str()); + log_file_error(attr->filename, attr->location.first_line, "Attribute `%s' with non-constant value!\n", id.c_str()); return attr->integer != 0; } @@ -195,13 +197,13 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch this->type = type; filename = current_filename; - linenum = get_line_num(); is_input = false; is_output = false; is_reg = false; is_logic = false; is_signed = false; is_string = false; + is_enum = false; is_wand = false; is_wor = false; is_unsized = false; @@ -277,7 +279,8 @@ void AstNode::dumpAst(FILE *f, std::string indent) const } std::string type_name = type2str(type); - fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum); + fprintf(f, "%s%s <%s:%d.%d-%d.%d>", indent.c_str(), type_name.c_str(), filename.c_str(), location.first_line, + location.first_column, location.last_line, location.last_column); if (!flag_no_dump_ptr) { if (id2ast) @@ -321,6 +324,9 @@ void AstNode::dumpAst(FILE *f, std::string indent) const fprintf(f, " %d", v); fprintf(f, " ]"); } + if (is_enum) { + fprintf(f, " type=enum"); + } fprintf(f, "\n"); for (auto &it : attributes) { @@ -933,20 +939,22 @@ RTLIL::Const AstNode::realAsConst(int width) } // create a new AstModule from an AST_MODULE AST node -static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL) +static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false) { log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE); if (defer) log("Storing AST representation for module `%s'.\n", ast->str.c_str()); - else + else if (!quiet) { log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str()); + } current_module = new AstModule; current_module->ast = NULL; current_module->name = ast->str; - current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum); - current_module->set_bool_attribute("\\cells_not_processed"); + current_module->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, + ast->location.first_column, ast->location.last_line, ast->location.last_column); + current_module->set_bool_attribute(ID::cells_not_processed); current_ast_mod = ast; AstNode *ast_before_simplify; @@ -999,61 +1007,61 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast log("--- END OF AST DUMP ---\n"); } - if (flag_nowb && ast->attributes.count("\\whitebox")) { - delete ast->attributes.at("\\whitebox"); - ast->attributes.erase("\\whitebox"); + if (flag_nowb && ast->attributes.count(ID::whitebox)) { + delete ast->attributes.at(ID::whitebox); + ast->attributes.erase(ID::whitebox); } - if (ast->attributes.count("\\lib_whitebox")) { + if (ast->attributes.count(ID::lib_whitebox)) { if (!flag_lib || flag_nowb) { - delete ast->attributes.at("\\lib_whitebox"); - ast->attributes.erase("\\lib_whitebox"); + delete ast->attributes.at(ID::lib_whitebox); + ast->attributes.erase(ID::lib_whitebox); } else { - if (ast->attributes.count("\\whitebox")) { - delete ast->attributes.at("\\whitebox"); - ast->attributes.erase("\\whitebox"); + if (ast->attributes.count(ID::whitebox)) { + delete ast->attributes.at(ID::whitebox); + ast->attributes.erase(ID::whitebox); } - AstNode *n = ast->attributes.at("\\lib_whitebox"); - ast->attributes["\\whitebox"] = n; - ast->attributes.erase("\\lib_whitebox"); + AstNode *n = ast->attributes.at(ID::lib_whitebox); + ast->attributes[ID::whitebox] = n; + ast->attributes.erase(ID::lib_whitebox); } } - if (!blackbox_module && ast->attributes.count("\\blackbox")) { - AstNode *n = ast->attributes.at("\\blackbox"); + if (!blackbox_module && ast->attributes.count(ID::blackbox)) { + AstNode *n = ast->attributes.at(ID::blackbox); if (n->type != AST_CONSTANT) - log_file_error(ast->filename, ast->linenum, "Got blackbox attribute with non-constant value!\n"); + log_file_error(ast->filename, ast->location.first_line, "Got blackbox attribute with non-constant value!\n"); blackbox_module = n->asBool(); } - if (blackbox_module && ast->attributes.count("\\whitebox")) { - AstNode *n = ast->attributes.at("\\whitebox"); + if (blackbox_module && ast->attributes.count(ID::whitebox)) { + AstNode *n = ast->attributes.at(ID::whitebox); if (n->type != AST_CONSTANT) - log_file_error(ast->filename, ast->linenum, "Got whitebox attribute with non-constant value!\n"); + log_file_error(ast->filename, ast->location.first_line, "Got whitebox attribute with non-constant value!\n"); blackbox_module = !n->asBool(); } - if (ast->attributes.count("\\noblackbox")) { + if (ast->attributes.count(ID::noblackbox)) { if (blackbox_module) { - AstNode *n = ast->attributes.at("\\noblackbox"); + AstNode *n = ast->attributes.at(ID::noblackbox); if (n->type != AST_CONSTANT) - log_file_error(ast->filename, ast->linenum, "Got noblackbox attribute with non-constant value!\n"); + log_file_error(ast->filename, ast->location.first_line, "Got noblackbox attribute with non-constant value!\n"); blackbox_module = !n->asBool(); } - delete ast->attributes.at("\\noblackbox"); - ast->attributes.erase("\\noblackbox"); + delete ast->attributes.at(ID::noblackbox); + ast->attributes.erase(ID::noblackbox); } if (blackbox_module) { - if (ast->attributes.count("\\whitebox")) { - delete ast->attributes.at("\\whitebox"); - ast->attributes.erase("\\whitebox"); + if (ast->attributes.count(ID::whitebox)) { + delete ast->attributes.at(ID::whitebox); + ast->attributes.erase(ID::whitebox); } - if (ast->attributes.count("\\lib_whitebox")) { - delete ast->attributes.at("\\lib_whitebox"); - ast->attributes.erase("\\lib_whitebox"); + if (ast->attributes.count(ID::lib_whitebox)) { + delete ast->attributes.at(ID::lib_whitebox); + ast->attributes.erase(ID::lib_whitebox); } std::vector<AstNode*> new_children; @@ -1074,8 +1082,8 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast ast->children.swap(new_children); - if (ast->attributes.count("\\blackbox") == 0) { - ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false); + if (ast->attributes.count(ID::blackbox) == 0) { + ast->attributes[ID::blackbox] = AstNode::mkconst_int(1, false); } } @@ -1083,7 +1091,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast for (auto &attr : ast->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + log_file_error(ast->filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); current_module->attributes[attr.first] = attr.second->asAttrConst(); } for (size_t i = 0; i < ast->children.size(); i++) { @@ -1116,7 +1124,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast } if (ast->type == AST_INTERFACE) - current_module->set_bool_attribute("\\is_interface"); + current_module->set_bool_attribute(ID::is_interface); current_module->ast = ast_before_simplify; current_module->nolatches = flag_nolatches; current_module->nomeminit = flag_nomeminit; @@ -1171,10 +1179,19 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump for (auto n : design->verilog_globals) (*it)->children.push_back(n->clone()); - for (auto n : design->verilog_packages){ - for (auto o : n->children) { + // append nodes from previous packages using package-qualified names + for (auto &n : design->verilog_packages) { + for (auto &o : n->children) { AstNode *cloned_node = o->clone(); - cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1); + // log("cloned node %s\n", type2str(cloned_node->type).c_str()); + if (cloned_node->type == AST_ENUM) { + for (auto &e : cloned_node->children) { + log_assert(e->type == AST_ENUM_ITEM); + e->str = n->str + std::string("::") + e->str.substr(1); + } + } else { + cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1); + } (*it)->children.push_back(cloned_node); } } @@ -1188,25 +1205,31 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump if (design->has((*it)->str)) { RTLIL::Module *existing_mod = design->module((*it)->str); if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) { - log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", (*it)->str.c_str()); + log_file_error((*it)->filename, (*it)->location.first_line, "Re-definition of module `%s'!\n", (*it)->str.c_str()); } else if (nooverwrite) { - log("Ignoring re-definition of module `%s' at %s:%d.\n", - (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); + log("Ignoring re-definition of module `%s' at %s:%d.%d-%d.%d.\n", + (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->location.first_line, (*it)->location.first_column, (*it)->location.last_line, (*it)->location.last_column); continue; } else { - log("Replacing existing%s module `%s' at %s:%d.\n", - existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", - (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); + log("Replacing existing%s module `%s' at %s:%d.%d-%d.%d.\n", + existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", + (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->location.first_line, (*it)->location.first_column, (*it)->location.last_line, (*it)->location.last_column); design->remove(existing_mod); } } design->add(process_module(*it, defer)); } - else if ((*it)->type == AST_PACKAGE) + else if ((*it)->type == AST_PACKAGE) { + // process enum/other declarations + (*it)->simplify(true, false, false, 1, -1, false, false); design->verilog_packages.push_back((*it)->clone()); - else + } + else { + // must be global definition + (*it)->simplify(false, false, false, 1, -1, false, false); //process enum/other declarations design->verilog_globals.push_back((*it)->clone()); + } } } @@ -1261,9 +1284,9 @@ AstNode * AST::find_modport(AstNode *intf, std::string name) // Iterate over all wires in an interface and add them as wires in the AST module: void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport) { - for (auto &wire_it : intfmodule->wires_){ - AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true))); - std::string origname = log_id(wire_it.first); + for (auto w : intfmodule->wires()){ + AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true))); + std::string origname = log_id(w->name); std::string newname = intfname + "." + origname; wire->str = newname; if (modport != NULL) { @@ -1297,7 +1320,7 @@ void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule // When an interface instance is found in a module, the whole RTLIL for the module will be rederived again // from AST. The interface members are copied into the AST module with the prefix of the interface. -void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module*> local_interfaces) +void AstModule::reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module*> &local_interfaces) { loadconfig(); @@ -1306,9 +1329,9 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT for (auto &intf : local_interfaces) { std::string intfname = intf.first.str(); RTLIL::Module *intfmodule = intf.second; - for (auto &wire_it : intfmodule->wires_){ - AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true))); - std::string newname = log_id(wire_it.first); + for (auto w : intfmodule->wires()){ + AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true))); + std::string newname = log_id(w->name); newname = intfname + "." + newname; wire->str = newname; new_ast->children.push_back(wire); @@ -1332,7 +1355,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT std::pair<std::string,std::string> res = split_modport_from_type(ch->str); std::string interface_type = res.first; std::string interface_modport = res.second; // Is "", if no modport - if (design->modules_.count(interface_type) > 0) { + if (design->module(interface_type) != nullptr) { // Add a cell to the module corresponding to the interface port such that // it can further propagated down if needed: AstNode *celltype_for_intf = new AstNode(AST_CELLTYPE); @@ -1342,7 +1365,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT new_ast->children.push_back(cell_for_intf); // Get all members of this non-overridden dummy interface instance: - RTLIL::Module *intfmodule = design->modules_[interface_type]; // All interfaces should at this point in time (assuming + RTLIL::Module *intfmodule = design->module(interface_type); // All interfaces should at this point in time (assuming // reprocess_module is called from the hierarchy pass) be // present in design->modules_ AstModule *ast_module_of_interface = (AstModule*)intfmodule; @@ -1362,12 +1385,12 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT std::string original_name = this->name.str(); std::string changed_name = original_name + "_before_replacing_local_interfaces"; design->rename(this, changed_name); - this->set_bool_attribute("\\to_delete"); + this->set_bool_attribute(ID::to_delete); // Check if the module was the top module. If it was, we need to remove the top attribute and put it on the // new module. - if (this->get_bool_attribute("\\initial_top")) { - this->attributes.erase("\\initial_top"); + if (this->get_bool_attribute(ID::initial_top)) { + this->attributes.erase(ID::initial_top); is_top = true; } @@ -1377,15 +1400,15 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT design->add(newmod); RTLIL::Module* mod = design->module(original_name); if (is_top) - mod->set_bool_attribute("\\top"); + mod->set_bool_attribute(ID::top); // Set the attribute "interfaces_replaced_in_module" so that it does not happen again. - mod->set_bool_attribute("\\interfaces_replaced_in_module"); + mod->set_bool_attribute(ID::interfaces_replaced_in_module); } // create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces // This method is used to explode the interface when the interface is a port of the module (not instantiated inside) -RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool /*mayfail*/) +RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool /*mayfail*/) { AstNode *new_ast = NULL; std::string modname = derive_common(design, parameters, &new_ast); @@ -1437,13 +1460,20 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R // Now that the interfaces have been exploded, we can delete the dummy port related to every interface. for(auto &intf : interfaces) { - if(mod->wires_.count(intf.first)) { - mod->wires_.erase(intf.first); + if(mod->wire(intf.first) != nullptr) { + // Normally, removing wires would be batched together as it's an + // expensive operation, however, in this case doing so would mean + // that a cell with the same name cannot be created (below)... + // Since we won't expect many interfaces to exist in a module, + // we can let this slide... + pool<RTLIL::Wire*> to_remove; + to_remove.insert(mod->wire(intf.first)); + mod->remove(to_remove); mod->fixup_ports(); - // We copy the cell of the interface to the sub-module such that it can further be found if it is propagated - // down to sub-sub-modules etc. - RTLIL::Cell * new_subcell = mod->addCell(intf.first, intf.second->name); - new_subcell->set_bool_attribute("\\is_interface"); + // We copy the cell of the interface to the sub-module such that it + // can further be found if it is propagated down to sub-sub-modules etc. + RTLIL::Cell *new_subcell = mod->addCell(intf.first, intf.second->name); + new_subcell->set_bool_attribute(ID::is_interface); } else { log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str()); @@ -1452,7 +1482,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R // If any interfaces were replaced, set the attribute 'interfaces_replaced_in_module': if (interfaces.size() > 0) { - mod->set_bool_attribute("\\interfaces_replaced_in_module"); + mod->set_bool_attribute(ID::interfaces_replaced_in_module); } } else { @@ -1464,16 +1494,18 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R } // create a new parametric module (when needed) and return the name of the generated module - without support for interfaces -RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool /*mayfail*/) +RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool /*mayfail*/) { + bool quiet = lib || attributes.count(ID::blackbox) || attributes.count(ID::whitebox); + AstNode *new_ast = NULL; - std::string modname = derive_common(design, parameters, &new_ast); + std::string modname = derive_common(design, parameters, &new_ast, quiet); if (!design->has(modname)) { new_ast->str = modname; - design->add(process_module(new_ast, false)); + design->add(process_module(new_ast, false, NULL, quiet)); design->module(modname)->check(); - } else { + } else if (!quiet) { log("Found cached RTLIL representation for module `%s'.\n", modname.c_str()); } @@ -1482,7 +1514,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R } // create a new parametric module (when needed) and return the name of the generated module -std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out) +std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, AstNode **new_ast_out, bool quiet) { std::string stripped_name = name.str(); @@ -1496,16 +1528,18 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString if (child->type != AST_PARAMETER) continue; para_counter++; - std::string para_id = child->str; - if (parameters.count(para_id) > 0) { - log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str]))); - para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id]))); + auto it = parameters.find(child->str); + if (it != parameters.end()) { + if (!quiet) + log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second)); + para_info += stringf("%s=%s", child->str.c_str(), log_signal(it->second)); continue; } - para_id = stringf("$%d", para_counter); - if (parameters.count(para_id) > 0) { - log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id]))); - para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id]))); + it = parameters.find(stringf("$%d", para_counter)); + if (it != parameters.end()) { + if (!quiet) + log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second)); + para_info += stringf("%s=%s", child->str.c_str(), log_signal(it->second)); continue; } } @@ -1521,47 +1555,56 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString if (design->has(modname)) return modname; - log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str()); + if (!quiet) + log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str()); loadconfig(); + pool<IdString> rewritten; + rewritten.reserve(GetSize(parameters)); + AstNode *new_ast = ast->clone(); para_counter = 0; for (auto child : new_ast->children) { if (child->type != AST_PARAMETER) continue; para_counter++; - std::string para_id = child->str; - if (parameters.count(para_id) > 0) { - log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str]))); + auto it = parameters.find(child->str); + if (it != parameters.end()) { + if (!quiet) + log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second)); goto rewrite_parameter; } - para_id = stringf("$%d", para_counter); - if (parameters.count(para_id) > 0) { - log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id]))); + it = parameters.find(stringf("$%d", para_counter)); + if (it != parameters.end()) { + if (!quiet) + log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second)); goto rewrite_parameter; } continue; rewrite_parameter: delete child->children.at(0); - if ((parameters[para_id].flags & RTLIL::CONST_FLAG_REAL) != 0) { + if ((it->second.flags & RTLIL::CONST_FLAG_REAL) != 0) { child->children[0] = new AstNode(AST_REALVALUE); - child->children[0]->realvalue = std::stod(parameters[para_id].decode_string()); - } else if ((parameters[para_id].flags & RTLIL::CONST_FLAG_STRING) != 0) - child->children[0] = AstNode::mkconst_str(parameters[para_id].decode_string()); + child->children[0]->realvalue = std::stod(it->second.decode_string()); + } else if ((it->second.flags & RTLIL::CONST_FLAG_STRING) != 0) + child->children[0] = AstNode::mkconst_str(it->second.decode_string()); else - child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, (parameters[para_id].flags & RTLIL::CONST_FLAG_SIGNED) != 0); - parameters.erase(para_id); + child->children[0] = AstNode::mkconst_bits(it->second.bits, (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0); + rewritten.insert(it->first); } - for (auto param : parameters) { - AstNode *defparam = new AstNode(AST_DEFPARAM, new AstNode(AST_IDENTIFIER)); - defparam->children[0]->str = param.first.str(); - if ((param.second.flags & RTLIL::CONST_FLAG_STRING) != 0) - defparam->children.push_back(AstNode::mkconst_str(param.second.decode_string())); - else - defparam->children.push_back(AstNode::mkconst_bits(param.second.bits, (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0)); - new_ast->children.push_back(defparam); - } + if (GetSize(rewritten) < GetSize(parameters)) + for (const auto ¶m : parameters) { + if (rewritten.count(param.first)) + continue; + AstNode *defparam = new AstNode(AST_DEFPARAM, new AstNode(AST_IDENTIFIER)); + defparam->children[0]->str = param.first.str(); + if ((param.second.flags & RTLIL::CONST_FLAG_STRING) != 0) + defparam->children.push_back(AstNode::mkconst_str(param.second.decode_string())); + else + defparam->children.push_back(AstNode::mkconst_bits(param.second.bits, (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0)); + new_ast->children.push_back(defparam); + } (*new_ast_out) = new_ast; return modname; @@ -1607,25 +1650,6 @@ void AstModule::loadconfig() const flag_icells = icells; flag_pwires = pwires; flag_autowire = autowire; - use_internal_line_num(); -} - -// internal dummy line number callbacks -namespace { - int internal_line_num; - void internal_set_line_num(int n) { - internal_line_num = n; - } - int internal_get_line_num() { - return internal_line_num; - } -} - -// use internal dummy line number callbacks -void AST::use_internal_line_num() -{ - set_line_num = &internal_set_line_num; - get_line_num = &internal_get_line_num; } YOSYS_NAMESPACE_END diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 14e1cec5e..3dd40238f 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -68,6 +68,8 @@ namespace AST AST_LIVE, AST_FAIR, AST_COVER, + AST_ENUM, + AST_ENUM_ITEM, AST_FCALL, AST_TO_BITS, @@ -154,6 +156,13 @@ namespace AST AST_TYPEDEF }; + struct AstSrcLocType { + unsigned int first_line, last_line; + unsigned int first_column, last_column; + AstSrcLocType() : first_line(0), last_line(0), first_column(0), last_column(0) {} + AstSrcLocType(int _first_line, int _first_column, int _last_line, int _last_column) : first_line(_first_line), last_line(_last_line), first_column(_first_column), last_column(_last_column) {} + }; + // convert an node type to a string (e.g. for debug output) std::string type2str(AstNodeType type); @@ -181,6 +190,8 @@ namespace AST int port_id, range_left, range_right; uint32_t integer; double realvalue; + // set for IDs typed to an enumeration, not used + bool is_enum; // if this is a multirange memory then this vector contains offset and length of each dimension std::vector<int> multirange_dimensions; @@ -195,7 +206,7 @@ namespace AST // it is automatically set by the constructor using AST::current_filename and // the AST::get_line_num() callback function. std::string filename; - int linenum; + AstSrcLocType location; // creating and deleting nodes AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL, AstNode *child3 = NULL); @@ -286,6 +297,9 @@ namespace AST int isConst() const; // return '1' for AST_CONSTANT and '2' for AST_REALVALUE double asReal(bool is_signed); RTLIL::Const realAsConst(int width); + + // helpers for enum + void allocateDefaultEnumValues(); }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code @@ -298,10 +312,10 @@ namespace AST AstNode *ast; bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire; ~AstModule() YS_OVERRIDE; - RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE; - RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail) YS_OVERRIDE; - std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out); - void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE; + RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool mayfail) YS_OVERRIDE; + RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) YS_OVERRIDE; + std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, AstNode **new_ast_out, bool quiet = false); + void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) YS_OVERRIDE; RTLIL::Module *clone() const YS_OVERRIDE; void loadconfig() const; }; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 94f5c0a04..c0539252c 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -41,30 +41,28 @@ using namespace AST; using namespace AST_INTERNAL; // helper function for creating RTLIL code for unary operations -static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true) +static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true) { - std::stringstream sstr; - sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++); - - RTLIL::Cell *cell = current_module->addCell(sstr.str(), type); - cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum); + IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++); + RTLIL::Cell *cell = current_module->addCell(name, type); + cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width); - wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum); + wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); if (gen_attributes) for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } - cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size()); - cell->setPort("\\A", arg); + cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed); + cell->parameters[ID::A_WIDTH] = RTLIL::Const(arg.size()); + cell->setPort(ID::A, arg); - cell->parameters["\\Y_WIDTH"] = result_width; - cell->setPort("\\Y", wire); + cell->parameters[ID::Y_WIDTH] = result_width; + cell->setPort(ID::Y, wire); return wire; } @@ -76,60 +74,56 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s return; } - std::stringstream sstr; - sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++); - - RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos"); - cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum); + IdString name = stringf("$extend$%s:%d$%d", that->filename.c_str(), that->location.first_line, autoidx++); + RTLIL::Cell *cell = current_module->addCell(name, ID($pos)); + cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width); - wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum); + wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); if (that != NULL) for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } - cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size()); - cell->setPort("\\A", sig); + cell->parameters[ID::A_SIGNED] = RTLIL::Const(is_signed); + cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size()); + cell->setPort(ID::A, sig); - cell->parameters["\\Y_WIDTH"] = width; - cell->setPort("\\Y", wire); + cell->parameters[ID::Y_WIDTH] = width; + cell->setPort(ID::Y, wire); sig = wire; } // helper function for creating RTLIL code for binary operations -static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) +static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) { - std::stringstream sstr; - sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++); - - RTLIL::Cell *cell = current_module->addCell(sstr.str(), type); - cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum); + IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++); + RTLIL::Cell *cell = current_module->addCell(name, type); + cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width); - wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum); + wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } - cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed); - cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed); + cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed); + cell->parameters[ID::B_SIGNED] = RTLIL::Const(that->children[1]->is_signed); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size()); - cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size()); + cell->parameters[ID::A_WIDTH] = RTLIL::Const(left.size()); + cell->parameters[ID::B_WIDTH] = RTLIL::Const(right.size()); - cell->setPort("\\A", left); - cell->setPort("\\B", right); + cell->setPort(ID::A, left); + cell->setPort(ID::B, right); - cell->parameters["\\Y_WIDTH"] = result_width; - cell->setPort("\\Y", wire); + cell->parameters[ID::Y_WIDTH] = result_width; + cell->setPort(ID::Y, wire); return wire; } @@ -139,26 +133,26 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const log_assert(cond.size() == 1); std::stringstream sstr; - sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (autoidx++); + sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++); - RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux"); - cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum); + RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux)); + cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size()); - wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum); + wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } - cell->parameters["\\WIDTH"] = RTLIL::Const(left.size()); + cell->parameters[ID::WIDTH] = RTLIL::Const(left.size()); - cell->setPort("\\A", right); - cell->setPort("\\B", left); - cell->setPort("\\S", cond); - cell->setPort("\\Y", wire); + cell->setPort(ID::A, right); + cell->setPort(ID::B, left); + cell->setPort(ID::S, cond); + cell->setPort(ID::Y, wire); return wire; } @@ -199,11 +193,11 @@ struct AST_INTERNAL::ProcessGenerator { // generate process and simple root case proc = new RTLIL::Process; - proc->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum); - proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++); + proc->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column); + proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++); for (auto &attr : always->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(always->filename, always->linenum, "Attribute `%s' with non-constant value!\n", + log_file_error(always->filename, always->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); proc->attributes[attr.first] = attr.second->asAttrConst(); } @@ -221,7 +215,7 @@ struct AST_INTERNAL::ProcessGenerator for (auto child : always->children) { if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && - child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) { + child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk)) { found_global_syncs = true; } if (child->type == AST_EDGE) { @@ -234,8 +228,8 @@ struct AST_INTERNAL::ProcessGenerator if (found_anyedge_syncs) { if (found_global_syncs) - log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n"); - log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum); + log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n"); + log("Note: Assuming pure combinatorial block at %s:%d.%d-%d.%d in\n", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column); log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n"); log("use of @* instead of @(...) for better match of synthesis and simulation.\n"); } @@ -245,16 +239,16 @@ struct AST_INTERNAL::ProcessGenerator for (auto child : always->children) if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) { if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast && - child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) + child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk)) continue; found_clocked_sync = true; if (found_global_syncs || found_anyedge_syncs) - log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n"); + log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n"); RTLIL::SyncRule *syncrule = new RTLIL::SyncRule; syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn; syncrule->signal = child->children[0]->genRTLIL(); if (GetSize(syncrule->signal) != 1) - log_file_error(always->filename, always->linenum, "Found posedge/negedge event on a signal that is not 1 bit wide!\n"); + log_file_error(always->filename, always->location.first_line, "Found posedge/negedge event on a signal that is not 1 bit wide!\n"); addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true); proc->syncs.push_back(syncrule); } @@ -267,7 +261,7 @@ struct AST_INTERNAL::ProcessGenerator } // create initial assignments for the temporary signals - if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) { + if ((flag_nolatches || always->get_bool_attribute(ID::nolatches) || current_module->get_bool_attribute(ID::nolatches)) && !found_clocked_sync) { subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from))); } else { addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from); @@ -335,7 +329,7 @@ struct AST_INTERNAL::ProcessGenerator } while (current_module->wires_.count(wire_name) > 0); RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width); - wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum); + wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column); chunk.wire = wire; chunk.offset = 0; @@ -420,7 +414,7 @@ struct AST_INTERNAL::ProcessGenerator for (auto &lvalue_c : lvalue.chunks()) { RTLIL::SigSpec lhs = lvalue_c; RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width); - if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync")) + if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute(ID::nosync)) rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size()); remove_unwanted_lvalue_bits(lhs, rhs); actions.push_back(RTLIL::SigSig(lhs, rhs)); @@ -470,13 +464,13 @@ struct AST_INTERNAL::ProcessGenerator case AST_CASE: { RTLIL::SwitchRule *sw = new RTLIL::SwitchRule; - sw->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum); + sw->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column); sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap()); current_case->switches.push_back(sw); for (auto &attr : ast->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + log_file_error(ast->filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); sw->attributes[attr.first] = attr.second->asAttrConst(); } @@ -504,7 +498,7 @@ struct AST_INTERNAL::ProcessGenerator RTLIL::CaseRule *backup_case = current_case; current_case = new RTLIL::CaseRule; - current_case->attributes["\\src"] = stringf("%s:%d", child->filename.c_str(), child->linenum); + current_case->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column); last_generated_case = current_case; addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue); for (auto node : child->children) { @@ -525,7 +519,7 @@ struct AST_INTERNAL::ProcessGenerator subst_rvalue_map.restore(); } - if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) { + if (last_generated_case != NULL && ast->get_bool_attribute(ID::full_case) && default_case == NULL) { #if 0 // this is a valid transformation, but as optimization it is premature. // better: add a default case that assigns 'x' to everything, and let later @@ -554,16 +548,16 @@ struct AST_INTERNAL::ProcessGenerator break; case AST_WIRE: - log_file_error(ast->filename, ast->linenum, "Found reg declaration in block without label!\n"); + log_file_error(ast->filename, ast->location.first_line, "Found reg declaration in block without label!\n"); break; case AST_ASSIGN: - log_file_error(ast->filename, ast->linenum, "Found continous assignment in always/initial block!\n"); + log_file_error(ast->filename, ast->location.first_line, "Found continous assignment in always/initial block!\n"); break; case AST_PARAMETER: case AST_LOCALPARAM: - log_file_error(ast->filename, ast->linenum, "Found parameter declaration in block without label!\n"); + log_file_error(ast->filename, ast->location.first_line, "Found parameter declaration in block without label!\n"); break; case AST_NONE: @@ -595,6 +589,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun switch (type) { + case AST_NONE: + // unallocated enum, ignore + break; case AST_CONSTANT: width_hint = max(width_hint, int(bits.size())); if (!is_signed) @@ -611,8 +608,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (id_ast == NULL && current_scope.count(str)) id_ast = current_scope.at(str); if (!id_ast) - log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", str.c_str()); - if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM) { + log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", str.c_str()); + if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) { if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) { this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1; } else @@ -621,7 +618,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (id_ast->children[0]->type == AST_CONSTANT) this_width = id_ast->children[0]->bits.size(); else - log_file_error(filename, linenum, "Failed to detect width for parameter %s!\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to detect width for parameter %s!\n", str.c_str()); if (children.size() != 0) range = children[0]; } else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) { @@ -633,7 +630,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun // log("---\n"); // id_ast->dumpAst(NULL, "decl> "); // dumpAst(NULL, "ref> "); - log_file_error(filename, linenum, "Failed to detect width of signal access `%s'!\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to detect width of signal access `%s'!\n", str.c_str()); } } else { this_width = id_ast->range_left - id_ast->range_right + 1; @@ -644,12 +641,12 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun this_width = 32; } else if (id_ast->type == AST_MEMORY) { if (!id_ast->children[0]->range_valid) - log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", str.c_str()); this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1; if (children.size() > 1) range = children[1]; } else - log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to detect width for identifier %s!\n", str.c_str()); if (range) { if (range->children.size() == 1) this_width = 1; @@ -659,7 +656,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); + log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; delete left_at_zero_ast; delete right_at_zero_ast; @@ -675,7 +672,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun case AST_TO_BITS: while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { } if (children[0]->type != AST_CONSTANT) - log_file_error(filename, linenum, "Left operand of tobits expression is not constant!\n"); + log_file_error(filename, location.first_line, "Left operand of tobits expression is not constant!\n"); children[1]->detectSignWidthWorker(sub_width_hint, sign_hint); width_hint = max(width_hint, children[0]->bitsAsConst().as_int()); break; @@ -703,7 +700,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun case AST_REPLICATE: while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { } if (children[0]->type != AST_CONSTANT) - log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n"); + log_file_error(filename, location.first_line, "Left operand of replicate expression is not constant!\n"); children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint); width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint); sign_hint = false; @@ -777,7 +774,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (!id2ast->is_signed) sign_hint = false; if (!id2ast->children[0]->range_valid) - log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", str.c_str()); this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1; width_hint = max(width_hint, this_width); break; @@ -787,7 +784,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (GetSize(children) == 1) { while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { } if (children[0]->type != AST_CONSTANT) - log_file_error(filename, linenum, "System function %s called with non-const argument!\n", + log_file_error(filename, location.first_line, "System function %s called with non-const argument!\n", RTLIL::unescape_id(str).c_str()); width_hint = max(width_hint, int(children[0]->asInt(true))); } @@ -809,7 +806,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun default: for (auto f : log_files) current_ast_mod->dumpAst(f, "verilog-ast> "); - log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str()); + log_file_error(filename, location.first_line, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str()); } if (*found_real) @@ -839,10 +836,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this // cases this variable is used to hold the type of the cell that should // be instantiated for this type of AST node. - std::string type_name; + IdString type_name; current_filename = filename; - set_line_num(linenum); switch (type) { @@ -861,6 +857,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_GENIF: case AST_GENCASE: case AST_PACKAGE: + case AST_ENUM: case AST_MODPORT: case AST_MODPORTMEMBER: case AST_TYPEDEF: @@ -870,19 +867,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // This is used by the hierarchy pass to know when it can replace interface connection with the individual // signals. RTLIL::Wire *wire = current_module->addWire(str, 1); - wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); wire->start_offset = 0; wire->port_id = port_id; wire->port_input = true; wire->port_output = true; - wire->set_bool_attribute("\\is_interface"); + wire->set_bool_attribute(ID::is_interface); if (children.size() > 0) { for(size_t i=0; i<children.size();i++) { if(children[i]->type == AST_INTERFACEPORTTYPE) { std::pair<std::string,std::string> res = AST::split_modport_from_type(children[i]->str); - wire->attributes["\\interface_type"] = res.first; + wire->attributes[ID::interface_type] = res.first; if (res.second != "") - wire->attributes["\\interface_modport"] = res.second; + wire->attributes[ID::interface_modport] = res.second; break; } } @@ -901,18 +898,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (flag_pwires) { if (GetSize(children) < 1 || children[0]->type != AST_CONSTANT) - log_file_error(filename, linenum, "Parameter `%s' with non-constant value!\n", str.c_str()); + log_file_error(filename, location.first_line, "Parameter `%s' with non-constant value!\n", str.c_str()); RTLIL::Const val = children[0]->bitsAsConst(); RTLIL::Wire *wire = current_module->addWire(str, GetSize(val)); current_module->connect(wire, val); - wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); - wire->attributes[type == AST_PARAMETER ? "\\parameter" : "\\localparam"] = 1; + wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); + wire->attributes[type == AST_PARAMETER ? ID::parameter : ID::localparam] = 1; for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); wire->attributes[attr.first] = attr.second->asAttrConst(); } } @@ -921,15 +918,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // create an RTLIL::Wire for an AST_WIRE node case AST_WIRE: { if (current_module->wires_.count(str) != 0) - log_file_error(filename, linenum, "Re-definition of signal `%s'!\n", str.c_str()); + log_file_error(filename, location.first_line, "Re-definition of signal `%s'!\n", str.c_str()); if (!range_valid) - log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n", str.c_str()); + log_file_error(filename, location.first_line, "Signal `%s' with non-constant width!\n", str.c_str()); if (!(range_left >= range_right || (range_left == -1 && range_right == 0))) - log_file_error(filename, linenum, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1); + log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1); RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1); - wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); wire->start_offset = range_right; wire->port_id = port_id; wire->port_input = is_input; @@ -938,29 +935,29 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); wire->attributes[attr.first] = attr.second->asAttrConst(); } - if (is_wand) wire->set_bool_attribute("\\wand"); - if (is_wor) wire->set_bool_attribute("\\wor"); + if (is_wand) wire->set_bool_attribute(ID::wand); + if (is_wor) wire->set_bool_attribute(ID::wor); } break; // create an RTLIL::Memory for an AST_MEMORY node case AST_MEMORY: { if (current_module->memories.count(str) != 0) - log_file_error(filename, linenum, "Re-definition of memory `%s'!\n", str.c_str()); + log_file_error(filename, location.first_line, "Re-definition of memory `%s'!\n", str.c_str()); log_assert(children.size() >= 2); log_assert(children[0]->type == AST_RANGE); log_assert(children[1]->type == AST_RANGE); if (!children[0]->range_valid || !children[1]->range_valid) - log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n", str.c_str()); + log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str()); RTLIL::Memory *memory = new RTLIL::Memory; - memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + memory->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); memory->name = str; memory->width = children[0]->range_left - children[0]->range_right + 1; if (children[1]->range_right < children[1]->range_left) { @@ -974,7 +971,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); memory->attributes[attr.first] = attr.second->asAttrConst(); } } @@ -997,7 +994,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } RTLIL::SigSpec sig = realAsConst(width_hint); - log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig)); + log_file_warning(filename, location.first_line, "converting real value %e to binary %s.\n", realvalue, log_signal(sig)); return sig; } @@ -1015,22 +1012,22 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) { RTLIL::Wire *wire = current_module->addWire(str); - wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); wire->name = str; if (flag_autowire) - log_file_warning(filename, linenum, "Identifier `%s' is implicitly declared.\n", str.c_str()); + log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str()); else - log_file_error(filename, linenum, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str()); + log_file_error(filename, location.first_line, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str()); } - else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) { + else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM || id2ast->type == AST_ENUM_ITEM) { if (id2ast->children[0]->type != AST_CONSTANT) - log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n", str.c_str()); + log_file_error(filename, location.first_line, "Parameter %s does not evaluate to constant value!\n", str.c_str()); chunk = RTLIL::Const(id2ast->children[0]->bits); goto use_const_chunk; } else if (id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) { RTLIL::Wire *current_wire = current_module->wire(str); - if (current_wire->get_bool_attribute("\\is_interface")) + if (current_wire->get_bool_attribute(ID::is_interface)) is_interface = true; // Ignore } @@ -1039,26 +1036,23 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) is_interface = true; } else { - log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n", str.c_str()); + log_file_error(filename, location.first_line, "Identifier `%s' doesn't map to any signal!\n", str.c_str()); } if (id2ast->type == AST_MEMORY) - log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n", str.c_str()); + log_file_error(filename, location.first_line, "Identifier `%s' does map to an unexpanded memory!\n", str.c_str()); // If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface' // This makes it possible for the hierarchy pass to see what are interface connections and then replace them // with the individual signals: if (is_interface) { - RTLIL::Wire *dummy_wire; - std::string dummy_wire_name = "$dummywireforinterface" + str; - if (current_module->wires_.count(dummy_wire_name)) - dummy_wire = current_module->wires_[dummy_wire_name]; - else { + IdString dummy_wire_name = stringf("$dummywireforinterface%s", str.c_str()); + RTLIL::Wire *dummy_wire = current_module->wire(dummy_wire_name); + if (!dummy_wire) { dummy_wire = current_module->addWire(dummy_wire_name); - dummy_wire->set_bool_attribute("\\is_interface"); + dummy_wire->set_bool_attribute(ID::is_interface); } - RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire); - return tmp; + return dummy_wire; } wire = current_module->wires_[str]; @@ -1069,7 +1063,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) use_const_chunk: if (children.size() != 0) { if (children[0]->type != AST_RANGE) - log_file_error(filename, linenum, "Single range expected.\n"); + log_file_error(filename, location.first_line, "Single range expected.\n"); int source_width = id2ast->range_left - id2ast->range_right + 1; int source_offset = id2ast->range_right; if (!children[0]->range_valid) { @@ -1078,7 +1072,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); + log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : children[0]->children[0]->clone()); @@ -1094,7 +1088,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } if (GetSize(shift_val) >= 32) fake_ast->children[1]->is_signed = true; - RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val); + RTLIL::SigSpec sig = binop2rtlil(fake_ast, ID($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val); delete left_at_zero_ast; delete right_at_zero_ast; delete fake_ast; @@ -1106,10 +1100,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width); if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) { if (chunk.width == 1) - log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n", + log_file_warning(filename, location.first_line, "Range select out of bounds on signal `%s': Setting result bit to undef.\n", str.c_str()); else - log_file_warning(filename, linenum, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n", + log_file_warning(filename, location.first_line, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n", children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width); chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width); } else { @@ -1123,10 +1117,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) chunk.offset += add_undef_bits_lsb; } if (add_undef_bits_lsb) - log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n", + log_file_warning(filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n", children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb); if (add_undef_bits_msb) - log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n", + log_file_warning(filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n", children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb); } } @@ -1166,7 +1160,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::SigSpec left = children[0]->genRTLIL(); RTLIL::SigSpec right = children[1]->genRTLIL(); if (!left.is_fully_const()) - log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n"); + log_file_error(filename, location.first_line, "Left operand of replicate expression is not constant!\n"); int count = left.as_int(); RTLIL::SigSpec sig; for (int i = 0; i < count; i++) @@ -1178,9 +1172,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } // generate cells for unary operations: $not, $pos, $neg - if (0) { case AST_BIT_NOT: type_name = "$not"; } - if (0) { case AST_POS: type_name = "$pos"; } - if (0) { case AST_NEG: type_name = "$neg"; } + if (0) { case AST_BIT_NOT: type_name = ID($not); } + if (0) { case AST_POS: type_name = ID($pos); } + if (0) { case AST_NEG: type_name = ID($neg); } { RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint); is_signed = children[0]->is_signed; @@ -1193,10 +1187,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } // generate cells for binary operations: $and, $or, $xor, $xnor - if (0) { case AST_BIT_AND: type_name = "$and"; } - if (0) { case AST_BIT_OR: type_name = "$or"; } - if (0) { case AST_BIT_XOR: type_name = "$xor"; } - if (0) { case AST_BIT_XNOR: type_name = "$xnor"; } + if (0) { case AST_BIT_AND: type_name = ID($and); } + if (0) { case AST_BIT_OR: type_name = ID($or); } + if (0) { case AST_BIT_XOR: type_name = ID($xor); } + if (0) { case AST_BIT_XNOR: type_name = ID($xnor); } { if (width_hint < 0) detectSignWidth(width_hint, sign_hint); @@ -1210,10 +1204,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } // generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor - if (0) { case AST_REDUCE_AND: type_name = "$reduce_and"; } - if (0) { case AST_REDUCE_OR: type_name = "$reduce_or"; } - if (0) { case AST_REDUCE_XOR: type_name = "$reduce_xor"; } - if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; } + if (0) { case AST_REDUCE_AND: type_name = ID($reduce_and); } + if (0) { case AST_REDUCE_OR: type_name = ID($reduce_or); } + if (0) { case AST_REDUCE_XOR: type_name = ID($reduce_xor); } + if (0) { case AST_REDUCE_XNOR: type_name = ID($reduce_xnor); } { RTLIL::SigSpec arg = children[0]->genRTLIL(); RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg); @@ -1222,7 +1216,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // generate cells for unary operations: $reduce_bool // (this is actually just an $reduce_or, but for clarity a different cell type is used) - if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; } + if (0) { case AST_REDUCE_BOOL: type_name = ID($reduce_bool); } { RTLIL::SigSpec arg = children[0]->genRTLIL(); RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg; @@ -1230,10 +1224,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } // generate cells for binary operations: $shl, $shr, $sshl, $sshr - if (0) { case AST_SHIFT_LEFT: type_name = "$shl"; } - if (0) { case AST_SHIFT_RIGHT: type_name = "$shr"; } - if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; } - if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; } + if (0) { case AST_SHIFT_LEFT: type_name = ID($shl); } + if (0) { case AST_SHIFT_RIGHT: type_name = ID($shr); } + if (0) { case AST_SHIFT_SLEFT: type_name = ID($sshl); } + if (0) { case AST_SHIFT_SRIGHT: type_name = ID($sshr); } { if (width_hint < 0) detectSignWidth(width_hint, sign_hint); @@ -1257,19 +1251,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int width = width_hint > 0 ? width_hint : left.size(); is_signed = children[0]->is_signed; if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed) - return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.size()), right); - return binop2rtlil(this, "$pow", width, left, right); + return binop2rtlil(this, ID($shl), width, RTLIL::SigSpec(1, left.size()), right); + return binop2rtlil(this, ID($pow), width, left, right); } // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt - if (0) { case AST_LT: type_name = "$lt"; } - if (0) { case AST_LE: type_name = "$le"; } - if (0) { case AST_EQ: type_name = "$eq"; } - if (0) { case AST_NE: type_name = "$ne"; } - if (0) { case AST_EQX: type_name = "$eqx"; } - if (0) { case AST_NEX: type_name = "$nex"; } - if (0) { case AST_GE: type_name = "$ge"; } - if (0) { case AST_GT: type_name = "$gt"; } + if (0) { case AST_LT: type_name = ID($lt); } + if (0) { case AST_LE: type_name = ID($le); } + if (0) { case AST_EQ: type_name = ID($eq); } + if (0) { case AST_NE: type_name = ID($ne); } + if (0) { case AST_EQX: type_name = ID($eqx); } + if (0) { case AST_NEX: type_name = ID($nex); } + if (0) { case AST_GE: type_name = ID($ge); } + if (0) { case AST_GT: type_name = ID($gt); } { int width = max(width_hint, 1); width_hint = -1, sign_hint = true; @@ -1282,11 +1276,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } // generate cells for binary operations: $add, $sub, $mul, $div, $mod - if (0) { case AST_ADD: type_name = "$add"; } - if (0) { case AST_SUB: type_name = "$sub"; } - if (0) { case AST_MUL: type_name = "$mul"; } - if (0) { case AST_DIV: type_name = "$div"; } - if (0) { case AST_MOD: type_name = "$mod"; } + if (0) { case AST_ADD: type_name = ID($add); } + if (0) { case AST_SUB: type_name = ID($sub); } + if (0) { case AST_MUL: type_name = ID($mul); } + if (0) { case AST_DIV: type_name = ID($div); } + if (0) { case AST_MOD: type_name = ID($mod); } { if (width_hint < 0) detectSignWidth(width_hint, sign_hint); @@ -1312,8 +1306,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } // generate cells for binary operations: $logic_and, $logic_or - if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; } - if (0) { case AST_LOGIC_OR: type_name = "$logic_or"; } + if (0) { case AST_LOGIC_AND: type_name = ID($logic_and); } + if (0) { case AST_LOGIC_OR: type_name = ID($logic_or); } { RTLIL::SigSpec left = children[0]->genRTLIL(); RTLIL::SigSpec right = children[1]->genRTLIL(); @@ -1324,7 +1318,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_LOGIC_NOT: { RTLIL::SigSpec arg = children[0]->genRTLIL(); - return uniop2rtlil(this, "$logic_not", max(width_hint, 1), arg); + return uniop2rtlil(this, ID($logic_not), max(width_hint, 1), arg); } // generate multiplexer for ternary operator (aka ?:-operator) @@ -1334,18 +1328,31 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) detectSignWidth(width_hint, sign_hint); RTLIL::SigSpec cond = children[0]->genRTLIL(); - RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint); - RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint); + RTLIL::SigSpec sig; + if (cond.is_fully_const()) { + if (cond.as_bool()) { + sig = children[1]->genRTLIL(width_hint, sign_hint); + widthExtend(this, sig, sig.size(), children[1]->is_signed); + } + else { + sig = children[2]->genRTLIL(width_hint, sign_hint); + widthExtend(this, sig, sig.size(), children[2]->is_signed); + } + } + else { + RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint); + RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint); - if (cond.size() > 1) - cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false); + if (cond.size() > 1) + cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false); - int width = max(val1.size(), val2.size()); - is_signed = children[1]->is_signed && children[2]->is_signed; - widthExtend(this, val1, width, is_signed); - widthExtend(this, val2, width, is_signed); + int width = max(val1.size(), val2.size()); + is_signed = children[1]->is_signed && children[2]->is_signed; + widthExtend(this, val1, width, is_signed); + widthExtend(this, val2, width, is_signed); - RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2); + sig = mux2rtlil(this, cond, val1, val2); + } if (sig.size() < width_hint) sig.extend_u0(width_hint, sign_hint); @@ -1356,13 +1363,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_MEMRD: { std::stringstream sstr; - sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++); + sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); - RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd"); - cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd)); + cell->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width); - wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + wire->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line); int mem_width, mem_size, addr_bits; is_signed = id2ast->is_signed; @@ -1370,18 +1377,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::SigSpec addr_sig = children[0]->genRTLIL(); - cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1)); - cell->setPort("\\EN", RTLIL::SigSpec(RTLIL::State::Sx, 1)); - cell->setPort("\\ADDR", addr_sig); - cell->setPort("\\DATA", RTLIL::SigSpec(wire)); + cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1)); + cell->setPort(ID::EN, RTLIL::SigSpec(RTLIL::State::Sx, 1)); + cell->setPort(ID::ADDR, addr_sig); + cell->setPort(ID::DATA, RTLIL::SigSpec(wire)); - cell->parameters["\\MEMID"] = RTLIL::Const(str); - cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig)); - cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width); + cell->parameters[ID::MEMID] = RTLIL::Const(str); + cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig)); + cell->parameters[ID::WIDTH] = RTLIL::Const(wire->width); - cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0); - cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0); - cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); + cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(0); + cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(0); + cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0); if (!sign_hint) is_signed = false; @@ -1394,10 +1401,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_MEMINIT: { std::stringstream sstr; - sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << linenum << "$" << (autoidx++); + sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); - RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit"); - cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? ID($memwr) : ID($meminit)); + cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); int mem_width, mem_size, addr_bits; id2ast->meminfo(mem_width, mem_size, addr_bits); @@ -1405,28 +1412,28 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int num_words = 1; if (type == AST_MEMINIT) { if (children[2]->type != AST_CONSTANT) - log_file_error(filename, linenum, "Memory init with non-constant word count!\n"); + log_file_error(filename, location.first_line, "Memory init with non-constant word count!\n"); num_words = int(children[2]->asInt(false)); - cell->parameters["\\WORDS"] = RTLIL::Const(num_words); + cell->parameters[ID::WORDS] = RTLIL::Const(num_words); } SigSpec addr_sig = children[0]->genRTLIL(); - cell->setPort("\\ADDR", addr_sig); - cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words)); + cell->setPort(ID::ADDR, addr_sig); + cell->setPort(ID::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words)); - cell->parameters["\\MEMID"] = RTLIL::Const(str); - cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig)); - cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width); + cell->parameters[ID::MEMID] = RTLIL::Const(str); + cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig)); + cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[str]->width); if (type == AST_MEMWR) { - cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1)); - cell->setPort("\\EN", children[2]->genRTLIL()); - cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0); - cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0); + cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1)); + cell->setPort(ID::EN, children[2]->genRTLIL()); + cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(0); + cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(0); } - cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1); + cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1); } break; @@ -1437,12 +1444,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_FAIR: case AST_COVER: { - const char *celltype = nullptr; - if (type == AST_ASSERT) celltype = "$assert"; - if (type == AST_ASSUME) celltype = "$assume"; - if (type == AST_LIVE) celltype = "$live"; - if (type == AST_FAIR) celltype = "$fair"; - if (type == AST_COVER) celltype = "$cover"; + IdString celltype; + if (type == AST_ASSERT) celltype = ID($assert); + if (type == AST_ASSUME) celltype = ID($assume); + if (type == AST_LIVE) celltype = ID($live); + if (type == AST_FAIR) celltype = ID($fair); + if (type == AST_COVER) celltype = ID($cover); log_assert(children.size() == 2); @@ -1455,25 +1462,22 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) en = current_module->ReduceBool(NEW_ID, en); IdString cellname; - if (str.empty()) { - std::stringstream sstr; - sstr << celltype << "$" << filename << ":" << linenum << "$" << (autoidx++); - cellname = sstr.str(); - } else { + if (str.empty()) + cellname = stringf("%s$%s:%d$%d", celltype.c_str(), filename.c_str(), location.first_line, autoidx++); + else cellname = str; - } RTLIL::Cell *cell = current_module->addCell(cellname, celltype); - cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } - cell->setPort("\\A", check); - cell->setPort("\\EN", en); + cell->setPort(ID::A, check); + cell->setPort(ID::EN, en); } break; @@ -1489,7 +1493,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) new_left.append(left[i]); new_right.append(right[i]); } - log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n" + log_file_warning(filename, location.first_line, "Ignoring assignment to constant bits:\n" " old assignment: %s = %s\n new assignment: %s = %s.\n", log_signal(left), log_signal(right), log_signal(new_left), log_signal(new_right)); @@ -1506,12 +1510,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int port_counter = 0, para_counter = 0; if (current_module->count_id(str) != 0) - log_file_error(filename, linenum, "Re-definition of cell `%s'!\n", str.c_str()); + log_file_error(filename, location.first_line, "Re-definition of cell `%s'!\n", str.c_str()); RTLIL::Cell *cell = current_module->addCell(str, ""); - cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass - cell->set_bool_attribute("\\module_not_derived"); + cell->set_bool_attribute(ID::module_not_derived); for (auto it = children.begin(); it != children.end(); it++) { AstNode *child = *it; @@ -1525,7 +1529,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int extra_const_flags = 0; IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str; if (child->children[0]->type == AST_REALVALUE) { - log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n", + log_file_warning(filename, location.first_line, "Replacing floating point parameter %s.%s = %f with string.\n", log_id(cell), log_id(paraname), child->children[0]->realvalue); extra_const_flags = RTLIL::CONST_FLAG_REAL; auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue)); @@ -1533,7 +1537,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) delete strnode; } if (child->children[0]->type != AST_CONSTANT) - log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n", + log_file_error(filename, location.first_line, "Parameter %s.%s with non-constant value!\n", log_id(cell), log_id(paraname)); cell->parameters[paraname] = child->children[0]->asParaConst(); cell->parameters[paraname].flags |= extra_const_flags; @@ -1556,28 +1560,32 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, linenum, "Attribute `%s' with non-constant value.\n", attr.first.c_str()); + log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value.\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } - if (cell->type.in("$specify2", "$specify3")) { - int src_width = GetSize(cell->getPort("\\SRC")); - int dst_width = GetSize(cell->getPort("\\DST")); - bool full = cell->getParam("\\FULL").as_bool(); + if (cell->type == ID($specify2)) { + int src_width = GetSize(cell->getPort(ID::SRC)); + int dst_width = GetSize(cell->getPort(ID::DST)); + bool full = cell->getParam(ID::FULL).as_bool(); if (!full && src_width != dst_width) - log_file_error(filename, linenum, "Parallel specify SRC width does not match DST width.\n"); - if (cell->type == "$specify3") { - int dat_width = GetSize(cell->getPort("\\DAT")); - if (dat_width != dst_width) - log_file_error(filename, linenum, "Specify DAT width does not match DST width.\n"); - } - cell->setParam("\\SRC_WIDTH", Const(src_width)); - cell->setParam("\\DST_WIDTH", Const(dst_width)); + log_file_error(filename, location.first_line, "Parallel specify SRC width does not match DST width.\n"); + cell->setParam(ID::SRC_WIDTH, Const(src_width)); + cell->setParam(ID::DST_WIDTH, Const(dst_width)); + } + else if (cell->type == ID($specify3)) { + int dat_width = GetSize(cell->getPort(ID::DAT)); + int dst_width = GetSize(cell->getPort(ID::DST)); + if (dat_width != dst_width) + log_file_error(filename, location.first_line, "Specify DAT width does not match DST width.\n"); + int src_width = GetSize(cell->getPort(ID::SRC)); + cell->setParam(ID::SRC_WIDTH, Const(src_width)); + cell->setParam(ID::DST_WIDTH, Const(dst_width)); } - if (cell->type == "$specrule") { - int src_width = GetSize(cell->getPort("\\SRC")); - int dst_width = GetSize(cell->getPort("\\DST")); - cell->setParam("\\SRC_WIDTH", Const(src_width)); - cell->setParam("\\DST_WIDTH", Const(dst_width)); + else if (cell->type == ID($specrule)) { + int src_width = GetSize(cell->getPort(ID::SRC)); + int dst_width = GetSize(cell->getPort(ID::DST)); + cell->setParam(ID::SRC_WIDTH, Const(src_width)); + cell->setParam(ID::DST_WIDTH, Const(dst_width)); } } break; @@ -1600,30 +1608,30 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int sz = children.size(); if (str == "$info") { if (sz > 0) - log_file_info(filename, linenum, "%s.\n", children[0]->str.c_str()); + log_file_info(filename, location.first_line, "%s.\n", children[0]->str.c_str()); else - log_file_info(filename, linenum, "\n"); + log_file_info(filename, location.first_line, "\n"); } else if (str == "$warning") { if (sz > 0) - log_file_warning(filename, linenum, "%s.\n", children[0]->str.c_str()); + log_file_warning(filename, location.first_line, "%s.\n", children[0]->str.c_str()); else - log_file_warning(filename, linenum, "\n"); + log_file_warning(filename, location.first_line, "\n"); } else if (str == "$error") { if (sz > 0) - log_file_error(filename, linenum, "%s.\n", children[0]->str.c_str()); + log_file_error(filename, location.first_line, "%s.\n", children[0]->str.c_str()); else - log_file_error(filename, linenum, "\n"); + log_file_error(filename, location.first_line, "\n"); } else if (str == "$fatal") { // TODO: 1st parameter, if exists, is 0,1 or 2, and passed to $finish() // if no parameter is given, default value is 1 // dollar_finish(sz ? children[0] : 1); // perhaps create & use log_file_fatal() if (sz > 0) - log_file_error(filename, linenum, "FATAL: %s.\n", children[0]->str.c_str()); + log_file_error(filename, location.first_line, "FATAL: %s.\n", children[0]->str.c_str()); else - log_file_error(filename, linenum, "FATAL.\n"); + log_file_error(filename, location.first_line, "FATAL.\n"); } else { - log_file_error(filename, linenum, "Unknown elabortoon system task '%s'.\n", str.c_str()); + log_file_error(filename, location.first_line, "Unknown elabortoon system task '%s'.\n", str.c_str()); } } break; @@ -1634,33 +1642,33 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int width = width_hint; if (GetSize(children) > 1) - log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 0.\n", + log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1 or 0.\n", RTLIL::unescape_id(str).c_str(), GetSize(children)); if (GetSize(children) == 1) { if (children[0]->type != AST_CONSTANT) - log_file_error(filename, linenum, "System function %s called with non-const argument!\n", + log_file_error(filename, location.first_line, "System function %s called with non-const argument!\n", RTLIL::unescape_id(str).c_str()); width = children[0]->asInt(true); } if (width <= 0) - log_file_error(filename, linenum, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str()); + log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str()); Cell *cell = current_module->addCell(myid, str.substr(1)); - cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); - cell->parameters["\\WIDTH"] = width; + cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); + cell->parameters[ID::WIDTH] = width; - if (attributes.count("\\reg")) { - auto &attr = attributes.at("\\reg"); + if (attributes.count(ID::reg)) { + auto &attr = attributes.at(ID::reg); if (attr->type != AST_CONSTANT) - log_file_error(filename, linenum, "Attribute `reg' with non-constant value!\n"); - cell->attributes["\\reg"] = attr->asAttrConst(); + log_file_error(filename, location.first_line, "Attribute `reg' with non-constant value!\n"); + cell->attributes[ID::reg] = attr->asAttrConst(); } Wire *wire = current_module->addWire(myid + "_wire", width); - wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); - cell->setPort("\\Y", wire); + wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); + cell->setPort(ID::Y, wire); is_signed = sign_hint; return SigSpec(wire); @@ -1672,7 +1680,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto f : log_files) current_ast_mod->dumpAst(f, "verilog-ast> "); type_name = type2str(type); - log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str()); + log_file_error(filename, location.first_line, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str()); } return RTLIL::SigSpec(); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 8855d9954..b87af0f8c 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -53,7 +53,7 @@ std::string AstNode::process_format_str(const std::string &sformat, int next_arg { // If there's no next character, that's a problem if (i+1 >= sformat.length()) - log_file_error(filename, linenum, "System task `%s' called with `%%' at end of string.\n", str.c_str()); + log_file_error(filename, location.first_line, "System task `%s' called with `%%' at end of string.\n", str.c_str()); char cformat = sformat[++i]; @@ -77,13 +77,13 @@ std::string AstNode::process_format_str(const std::string &sformat, int next_arg case 'x': case 'X': if (next_arg >= GetSize(children)) - log_file_error(filename, linenum, "Missing argument for %%%c format specifier in system task `%s'.\n", + log_file_error(filename, location.first_line, "Missing argument for %%%c format specifier in system task `%s'.\n", cformat, str.c_str()); node_arg = children[next_arg++]; while (node_arg->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (node_arg->type != AST_CONSTANT) - log_file_error(filename, linenum, "Failed to evaluate system task `%s' with non-constant argument.\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to evaluate system task `%s' with non-constant argument.\n", str.c_str()); break; case 'm': @@ -91,7 +91,7 @@ std::string AstNode::process_format_str(const std::string &sformat, int next_arg break; default: - log_file_error(filename, linenum, "System task `%s' called with invalid/unsupported format specifier.\n", str.c_str()); + log_file_error(filename, location.first_line, "System task `%s' called with invalid/unsupported format specifier.\n", str.c_str()); break; } @@ -159,7 +159,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, #if 0 log("-------------\n"); - log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, filename.c_str(), linenum, type2str(type).c_str(), this); + log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, filename.c_str(), location.first_line, type2str(type).c_str(), this); log("const_fold=%d, at_zero=%d, in_lvalue=%d, stage=%d, width_hint=%d, sign_hint=%d, in_param=%d\n", int(const_fold), int(at_zero), int(in_lvalue), int(stage), int(width_hint), int(sign_hint), int(in_param)); // dumpAst(NULL, "> "); @@ -172,7 +172,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, deep_recursion_warning = true; while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { } - if (!flag_nomem2reg && !get_bool_attribute("\\nomem2reg")) + if (!flag_nomem2reg && !get_bool_attribute(ID::nomem2reg)) { dict<AstNode*, pool<std::string>> mem2reg_places; dict<AstNode*, uint32_t> mem2reg_candidates, dummy_proc_flags; @@ -187,10 +187,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, bool this_nomeminit = flag_nomeminit; log_assert((memflags & ~0x00ffff00) == 0); - if (mem->get_bool_attribute("\\nomem2reg")) + if (mem->get_bool_attribute(ID::nomem2reg)) continue; - if (mem->get_bool_attribute("\\nomeminit") || get_bool_attribute("\\nomeminit")) + if (mem->get_bool_attribute(ID::nomeminit) || get_bool_attribute(ID::nomeminit)) this_nomeminit = true; if (memflags & AstNode::MEM2REG_FL_FORCED) @@ -248,10 +248,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, reg->is_reg = true; reg->is_signed = node->is_signed; for (auto &it : node->attributes) - if (it.first != ID(mem2reg)) + if (it.first != ID::mem2reg) reg->attributes.emplace(it.first, it.second->clone()); reg->filename = node->filename; - reg->linenum = node->linenum; + reg->location = node->location; children.push_back(reg); while (reg->simplify(true, false, false, 1, -1, false, false)) { } } @@ -273,7 +273,6 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } current_filename = filename; - set_line_num(linenum); // we do not look inside a task or function // (but as soon as a task or function is instantiated we process the generated AST as usual) @@ -286,13 +285,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // note that $display, $finish, and $stop are used for synthesis-time DRC so they're not in this list if ((type == AST_FCALL || type == AST_TCALL) && (str == "$strobe" || str == "$monitor" || str == "$time" || str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) { - log_file_warning(filename, linenum, "Ignoring call to system %s %s.\n", type == AST_FCALL ? "function" : "task", str.c_str()); + log_file_warning(filename, location.first_line, "Ignoring call to system %s %s.\n", type == AST_FCALL ? "function" : "task", str.c_str()); delete_children(); str = std::string(); } if ((type == AST_TCALL) && (str == "$display" || str == "$write") && (!current_always || current_always->type != AST_INITIAL)) { - log_file_warning(filename, linenum, "System task `%s' outside initial block is unsupported.\n", str.c_str()); + log_file_warning(filename, location.first_line, "System task `%s' outside initial block is unsupported.\n", str.c_str()); delete_children(); str = std::string(); } @@ -304,14 +303,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, { int nargs = GetSize(children); if (nargs < 1) - log_file_error(filename, linenum, "System task `%s' got %d arguments, expected >= 1.\n", + log_file_error(filename, location.first_line, "System task `%s' got %d arguments, expected >= 1.\n", str.c_str(), int(children.size())); // First argument is the format string AstNode *node_string = children[0]; while (node_string->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (node_string->type != AST_CONSTANT) - log_file_error(filename, linenum, "Failed to evaluate system task `%s' with non-constant 1st argument.\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to evaluate system task `%s' with non-constant 1st argument.\n", str.c_str()); std::string sformat = node_string->bitsAsConst().decode_string(); std::string sout = process_format_str(sformat, 1, stage, width_hint, sign_hint); // Finally, print the message (only include a \n for $display, not for $write) @@ -323,9 +322,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } // activate const folding if this is anything that must be evaluated statically (ranges, parameters, attributes, etc.) - if (type == AST_WIRE || type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_DEFPARAM || type == AST_PARASET || type == AST_RANGE || type == AST_PREFIX || type == AST_TYPEDEF) + if (type == AST_WIRE || type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_ENUM_ITEM || type == AST_DEFPARAM || type == AST_PARASET || type == AST_RANGE || type == AST_PREFIX || type == AST_TYPEDEF) const_fold = true; - if (type == AST_IDENTIFIER && current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM)) + if (type == AST_IDENTIFIER && current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM || current_scope[str]->type == AST_ENUM_ITEM)) const_fold = true; // in certain cases a function must be evaluated constant. this is what in_param controls. @@ -346,9 +345,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) { for (auto c : node->children[0]->children) { if (!c->is_simple_const_expr()) { - if (attributes.count("\\dynports")) - delete attributes.at("\\dynports"); - attributes["\\dynports"] = AstNode::mkconst_int(1, true); + if (attributes.count(ID::dynports)) + delete attributes.at(ID::dynports); + attributes[ID::dynports] = AstNode::mkconst_int(1, true); } } } @@ -405,23 +404,40 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, continue; wires_are_incompatible: if (stage > 1) - log_file_error(filename, linenum, "Incompatible re-declaration of wire %s.\n", node->str.c_str()); + log_file_error(filename, location.first_line, "Incompatible re-declaration of wire %s.\n", node->str.c_str()); continue; } this_wire_scope[node->str] = node; } + // these nodes appear at the top level in a module and can define names if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_GENVAR || node->type == AST_MEMORY || node->type == AST_FUNCTION || node->type == AST_TASK || node->type == AST_DPI_FUNCTION || node->type == AST_CELL || node->type == AST_TYPEDEF) { backup_scope[node->str] = current_scope[node->str]; current_scope[node->str] = node; } + if (node->type == AST_ENUM) { + current_scope[node->str] = node; + for (auto enode : node->children) { + log_assert(enode->type==AST_ENUM_ITEM); + if (current_scope.count(enode->str) == 0) { + current_scope[enode->str] = enode; + } + } + } } for (size_t i = 0; i < children.size(); i++) { AstNode *node = children[i]; if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY || node->type == AST_TYPEDEF) while (node->simplify(true, false, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM)) did_something = true; + if (node->type == AST_ENUM) { + for (auto enode YS_ATTRIBUTE(unused) : node->children){ + log_assert(enode->type==AST_ENUM_ITEM); + while (node->simplify(true, false, false, 1, -1, false, in_param)) + did_something = true; + } + } } } @@ -434,7 +450,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_ALWAYS || type == AST_INITIAL) { if (current_always != nullptr) - log_file_error(filename, linenum, "Invalid nesting of always blocks and/or initializations.\n"); + log_file_error(filename, location.first_line, "Invalid nesting of always blocks and/or initializations.\n"); current_always = this; current_always_clocked = false; @@ -477,7 +493,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->id2ast->is_logic) children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg) - log_warning("wire '%s' is assigned in a block at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum); + log_warning("wire '%s' is assigned in a block at %s:%d.%d-%d.%d.\n", children[0]->str.c_str(), filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); if (type == AST_ASSIGN && children[0]->id2ast->is_reg) { bool is_rand_reg = false; if (children[1]->type == AST_FCALL) { @@ -491,12 +507,24 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, is_rand_reg = true; } if (!is_rand_reg) - log_warning("reg '%s' is assigned in a continuous assignment at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum); + log_warning("reg '%s' is assigned in a continuous assignment at %s:%d.%d-%d.%d.\n", children[0]->str.c_str(), filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); } children[0]->was_checked = true; } break; + case AST_ENUM: + //log("\nENUM %s: %d child %d\n", str.c_str(), basic_prep, children[0]->basic_prep); + if (!basic_prep) { + for (auto item_node : children) { + while (!item_node->basic_prep && item_node->simplify(false, false, false, stage, -1, false, in_param)) + did_something = true; + } + // allocate values (called more than once) + allocateDefaultEnumValues(); + } + break; + case AST_PARAMETER: case AST_LOCALPARAM: while (!children[0]->basic_prep && children[0]->simplify(false, false, false, stage, -1, false, true) == true) @@ -506,7 +534,19 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, while (!children[1]->basic_prep && children[1]->simplify(false, false, false, stage, -1, false, true) == true) did_something = true; if (!children[1]->range_valid) - log_file_error(filename, linenum, "Non-constant width range on parameter decl.\n"); + log_file_error(filename, location.first_line, "Non-constant width range on parameter decl.\n"); + width_hint = max(width_hint, children[1]->range_left - children[1]->range_right + 1); + } + break; + case AST_ENUM_ITEM: + while (!children[0]->basic_prep && children[0]->simplify(false, false, false, stage, -1, false, in_param)) + did_something = true; + children[0]->detectSignWidth(width_hint, sign_hint); + if (children.size() > 1 && children[1]->type == AST_RANGE) { + while (!children[1]->basic_prep && children[1]->simplify(false, false, false, stage, -1, false, in_param)) + did_something = true; + if (!children[1]->range_valid) + log_file_error(filename, location.first_line, "Non-constant width range on enum item decl.\n"); width_hint = max(width_hint, children[1]->range_left - children[1]->range_right + 1); } break; @@ -745,7 +785,6 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } current_filename = filename; - set_line_num(linenum); if (type == AST_MODULE) current_scope.clear(); @@ -754,7 +793,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_DEFPARAM && !children.empty()) { if (children[0]->type != AST_IDENTIFIER) - log_file_error(filename, linenum, "Module name in defparam contains non-constant expressions!\n"); + log_file_error(filename, location.first_line, "Module name in defparam contains non-constant expressions!\n"); string modname, paramname = children[0]->str; @@ -771,12 +810,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } if (pos == std::string::npos) - log_file_error(filename, linenum, "Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname).c_str()); + log_file_error(filename, location.first_line, "Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname).c_str()); paramname = "\\" + paramname.substr(pos+1); if (current_scope.at(modname)->type != AST_CELL) - log_file_error(filename, linenum, "Defparam argument `%s . %s` does not match a cell!\n", + log_file_error(filename, location.first_line, "Defparam argument `%s . %s` does not match a cell!\n", RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str()); AstNode *paraset = new AstNode(AST_PARASET, children[1]->clone(), GetSize(children) > 2 ? children[2]->clone() : NULL); @@ -802,10 +841,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(children.size() >= 1); log_assert(children[0]->type == AST_WIRETYPE); if (!current_scope.count(children[0]->str)) - log_file_error(filename, linenum, "Unknown identifier `%s' used as type name\n", children[0]->str.c_str()); + log_file_error(filename, location.first_line, "Unknown identifier `%s' used as type name\n", children[0]->str.c_str()); AstNode *resolved_type = current_scope.at(children[0]->str); if (resolved_type->type != AST_TYPEDEF) - log_file_error(filename, linenum, "`%s' does not name a type\n", children[0]->str.c_str()); + log_file_error(filename, location.first_line, "`%s' does not name a type\n", children[0]->str.c_str()); log_assert(resolved_type->children.size() == 1); AstNode *templ = resolved_type->children[0]; // Remove type reference @@ -827,11 +866,68 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, range_swapped = templ->range_swapped; range_left = templ->range_left; range_right = templ->range_right; + attributes["\\wiretype"] = mkconst_str(resolved_type->str); + //check if enum + if (templ->attributes.count("\\enum_type")){ + //get reference to enum node: + std::string enum_type = templ->attributes["\\enum_type"]->str.c_str(); + // log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type)); + // log("current scope:\n"); + // for (auto &it : current_scope) + // log(" %s\n", it.first.c_str()); + log_assert(current_scope.count(enum_type) == 1); + AstNode *enum_node = current_scope.at(enum_type); + log_assert(enum_node->type == AST_ENUM); + //get width from 1st enum item: + log_assert(enum_node->children.size() >= 1); + AstNode *enum_item0 = enum_node->children[0]; + log_assert(enum_item0->type == AST_ENUM_ITEM); + int width; + if (!enum_item0->range_valid) + width = 1; + else if (enum_item0->range_swapped) + width = enum_item0->range_right - enum_item0->range_left + 1; + else + width = enum_item0->range_left - enum_item0->range_right + 1; + log_assert(width > 0); + //add declared enum items: + for (auto enum_item : enum_node->children){ + log_assert(enum_item->type == AST_ENUM_ITEM); + //get is_signed + bool is_signed; + if (enum_item->children.size() == 1){ + is_signed = false; + } else if (enum_item->children.size() == 2){ + log_assert(enum_item->children[1]->type == AST_RANGE); + is_signed = enum_item->children[1]->is_signed; + } else { + log_error("enum_item children size==%lu, expected 1 or 2 for %s (%s)\n", + enum_item->children.size(), + enum_item->str.c_str(), enum_node->str.c_str() + ); + } + //start building attribute string + std::string enum_item_str = "\\enum_"; + enum_item_str.append(std::to_string(width)); + enum_item_str.append("_"); + //get enum item value + if(enum_item->children[0]->type != AST_CONSTANT){ + log_error("expected const, got %s for %s (%s)\n", + type2str(enum_item->children[0]->type).c_str(), + enum_item->str.c_str(), enum_node->str.c_str() + ); + } + int val = enum_item->children[0]->asInt(is_signed); + enum_item_str.append(std::to_string(val)); + //set attribute for available val to enum item name mappings + attributes[enum_item_str.c_str()] = mkconst_str(enum_item->str); + } + } // Insert clones children from template at beginning for (int i = 0; i < GetSize(templ->children); i++) children.insert(children.begin() + i, templ->children[i]->clone()); - + if (type == AST_MEMORY && GetSize(children) == 1) { // Single-bit memories must have [0:0] range AstNode *rng = new AstNode(AST_RANGE); @@ -851,10 +947,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(children.size() == 2); log_assert(children[1]->type == AST_WIRETYPE); if (!current_scope.count(children[1]->str)) - log_file_error(filename, linenum, "Unknown identifier `%s' used as type name\n", children[1]->str.c_str()); + log_file_error(filename, location.first_line, "Unknown identifier `%s' used as type name\n", children[1]->str.c_str()); AstNode *resolved_type = current_scope.at(children[1]->str); if (resolved_type->type != AST_TYPEDEF) - log_file_error(filename, linenum, "`%s' does not name a type\n", children[1]->str.c_str()); + log_file_error(filename, location.first_line, "`%s' does not name a type\n", children[1]->str.c_str()); log_assert(resolved_type->children.size() == 1); AstNode *templ = resolved_type->children[0]; delete children[1]; @@ -864,7 +960,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, while(templ->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; if (templ->type == AST_MEMORY) - log_file_error(filename, linenum, "unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str()); + log_file_error(filename, location.first_line, "unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str()); is_signed = templ->is_signed; is_string = templ->is_string; is_custom_type = templ->is_custom_type; @@ -873,18 +969,19 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, range_swapped = templ->range_swapped; range_left = templ->range_left; range_right = templ->range_right; + attributes["\\wiretype"] = mkconst_str(resolved_type->str); for (auto template_child : templ->children) children.push_back(template_child->clone()); did_something = true; } log_assert(!is_custom_type); - } + } // resolve constant prefixes if (type == AST_PREFIX) { if (children[0]->type != AST_CONSTANT) { // dumpAst(NULL, "> "); - log_file_error(filename, linenum, "Index in generate block prefix syntax is not constant!\n"); + log_file_error(filename, location.first_line, "Index in generate block prefix syntax is not constant!\n"); } if (children[1]->type == AST_PREFIX) children[1]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param); @@ -900,9 +997,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // evaluate TO_BITS nodes if (type == AST_TO_BITS) { if (children[0]->type != AST_CONSTANT) - log_file_error(filename, linenum, "Left operand of to_bits expression is not constant!\n"); + log_file_error(filename, location.first_line, "Left operand of to_bits expression is not constant!\n"); if (children[1]->type != AST_CONSTANT) - log_file_error(filename, linenum, "Right operand of to_bits expression is not constant!\n"); + log_file_error(filename, location.first_line, "Right operand of to_bits expression is not constant!\n"); RTLIL::Const new_value = children[1]->bitsAsConst(children[0]->bitsAsConst().as_int(), children[1]->is_signed); newNode = mkconst_bits(new_value.bits, children[1]->is_signed); goto apply_newNode; @@ -966,7 +1063,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, multirange_dimensions.clear(); for (auto range : children[1]->children) { if (!range->range_valid) - log_file_error(filename, linenum, "Non-constant range on memory decl.\n"); + log_file_error(filename, location.first_line, "Non-constant range on memory decl.\n"); multirange_dimensions.push_back(min(range->range_left, range->range_right)); multirange_dimensions.push_back(max(range->range_left, range->range_right) - min(range->range_left, range->range_right) + 1); total_size *= multirange_dimensions.back(); @@ -984,7 +1081,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, for (int i = 0; 2*i < GetSize(id2ast->multirange_dimensions); i++) { if (GetSize(children[0]->children) < i) - log_file_error(filename, linenum, "Insufficient number of array indices for %s.\n", log_id(str)); + log_file_error(filename, location.first_line, "Insufficient number of array indices for %s.\n", log_id(str)); AstNode *new_index_expr = children[0]->children[i]->children.at(0)->clone(); @@ -1010,14 +1107,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } // trim/extend parameters - if (type == AST_PARAMETER || type == AST_LOCALPARAM) { + if (type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_ENUM_ITEM) { if (children.size() > 1 && children[1]->type == AST_RANGE) { if (!children[1]->range_valid) - log_file_error(filename, linenum, "Non-constant width range on parameter decl.\n"); + log_file_error(filename, location.first_line, "Non-constant width range on parameter decl.\n"); int width = std::abs(children[1]->range_left - children[1]->range_right) + 1; if (children[0]->type == AST_REALVALUE) { RTLIL::Const constvalue = children[0]->realAsConst(width); - log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", + log_file_warning(filename, location.first_line, "converting real value %e to binary %s.\n", children[0]->realvalue, log_signal(constvalue)); delete children[0]; children[0] = mkconst_bits(constvalue.bits, sign_hint); @@ -1051,9 +1148,34 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_IDENTIFIER) { if (current_scope.count(str) == 0) { for (auto node : current_ast_mod->children) { - if ((node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_GENVAR || - node->type == AST_MEMORY || node->type == AST_FUNCTION || node->type == AST_TASK || node->type == AST_DPI_FUNCTION) && str == node->str) { + //log("looking at mod scope child %s\n", type2str(node->type).c_str()); + switch (node->type) { + case AST_PARAMETER: + case AST_LOCALPARAM: + case AST_WIRE: + case AST_AUTOWIRE: + case AST_GENVAR: + case AST_MEMORY: + case AST_FUNCTION: + case AST_TASK: + case AST_DPI_FUNCTION: + //log("found child %s, %s\n", type2str(node->type).c_str(), node->str.c_str()); + if (str == node->str) { + //log("add %s, type %s to scope\n", str.c_str(), type2str(node->type).c_str()); + current_scope[node->str] = node; + } + break; + case AST_ENUM: current_scope[node->str] = node; + for (auto enum_node : node->children) { + log_assert(enum_node->type==AST_ENUM_ITEM); + if (str == enum_node->str) { + //log("\nadding enum item %s to scope\n", str.c_str()); + current_scope[str] = enum_node; + } + } + break; + default: break; } } @@ -1066,7 +1188,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, current_scope[str] = auto_wire; did_something = true; } else { - log_file_error(filename, linenum, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str()); + log_file_error(filename, location.first_line, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str()); } } if (id2ast != current_scope[str]) { @@ -1079,7 +1201,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_IDENTIFIER && children.size() == 2 && children[0]->type == AST_RANGE && children[1]->type == AST_RANGE && !in_lvalue) { if (id2ast == NULL || id2ast->type != AST_MEMORY || children[0]->children.size() != 1) - log_file_error(filename, linenum, "Invalid bit-select on memory access!\n"); + log_file_error(filename, location.first_line, "Invalid bit-select on memory access!\n"); int mem_width, mem_size, addr_bits; id2ast->meminfo(mem_width, mem_size, addr_bits); @@ -1091,13 +1213,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, std::swap(data_range_left, data_range_right); std::stringstream sstr; - sstr << "$mem2bits$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++); + sstr << "$mem2bits$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); std::string wire_id = sstr.str(); AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true))); wire->str = wire_id; if (current_block) - wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); current_ast_mod->children.push_back(wire); while (wire->simplify(true, false, false, 1, -1, false, false)) { } @@ -1132,7 +1254,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } if (type == AST_WHILE) - log_file_error(filename, linenum, "While loops are only allowed in constant functions!\n"); + log_file_error(filename, location.first_line, "While loops are only allowed in constant functions!\n"); if (type == AST_REPEAT) { @@ -1143,7 +1265,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, while (count->simplify(true, false, false, stage, 32, true, false)) { } if (count->type != AST_CONSTANT) - log_file_error(filename, linenum, "Repeat loops outside must have constant repeat counts!\n"); + log_file_error(filename, location.first_line, "Repeat loops outside must have constant repeat counts!\n"); // convert to a block with the body repeated n times type = AST_BLOCK; @@ -1169,24 +1291,24 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, body_ast = body_ast->children.at(0); if (init_ast->type != AST_ASSIGN_EQ) - log_file_error(filename, linenum, "Unsupported 1st expression of generate for-loop!\n"); + log_file_error(filename, location.first_line, "Unsupported 1st expression of generate for-loop!\n"); if (next_ast->type != AST_ASSIGN_EQ) - log_file_error(filename, linenum, "Unsupported 3rd expression of generate for-loop!\n"); + log_file_error(filename, location.first_line, "Unsupported 3rd expression of generate for-loop!\n"); if (type == AST_GENFOR) { if (init_ast->children[0]->id2ast == NULL || init_ast->children[0]->id2ast->type != AST_GENVAR) - log_file_error(filename, linenum, "Left hand side of 1st expression of generate for-loop is not a gen var!\n"); + log_file_error(filename, location.first_line, "Left hand side of 1st expression of generate for-loop is not a gen var!\n"); if (next_ast->children[0]->id2ast == NULL || next_ast->children[0]->id2ast->type != AST_GENVAR) - log_file_error(filename, linenum, "Left hand side of 3rd expression of generate for-loop is not a gen var!\n"); + log_file_error(filename, location.first_line, "Left hand side of 3rd expression of generate for-loop is not a gen var!\n"); } else { if (init_ast->children[0]->id2ast == NULL || init_ast->children[0]->id2ast->type != AST_WIRE) - log_file_error(filename, linenum, "Left hand side of 1st expression of generate for-loop is not a register!\n"); + log_file_error(filename, location.first_line, "Left hand side of 1st expression of generate for-loop is not a register!\n"); if (next_ast->children[0]->id2ast == NULL || next_ast->children[0]->id2ast->type != AST_WIRE) - log_file_error(filename, linenum, "Left hand side of 3rd expression of generate for-loop is not a register!\n"); + log_file_error(filename, location.first_line, "Left hand side of 3rd expression of generate for-loop is not a register!\n"); } if (init_ast->children[0]->id2ast != next_ast->children[0]->id2ast) - log_file_error(filename, linenum, "Incompatible left-hand sides in 1st and 3rd expression of generate for-loop!\n"); + log_file_error(filename, location.first_line, "Incompatible left-hand sides in 1st and 3rd expression of generate for-loop!\n"); // eval 1st expression AstNode *varbuf = init_ast->children[1]->clone(); @@ -1198,19 +1320,25 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } if (varbuf->type != AST_CONSTANT) - log_file_error(filename, linenum, "Right hand side of 1st expression of generate for-loop is not constant!\n"); - - varbuf = new AstNode(AST_LOCALPARAM, varbuf); - varbuf->str = init_ast->children[0]->str; + log_file_error(filename, location.first_line, "Right hand side of 1st expression of generate for-loop is not constant!\n"); auto resolved = current_scope.at(init_ast->children[0]->str); if (resolved->range_valid) { - varbuf->range_left = resolved->range_left; - varbuf->range_right = resolved->range_right; - varbuf->range_swapped = resolved->range_swapped; - varbuf->range_valid = resolved->range_valid; + int const_size = varbuf->range_left - varbuf->range_right; + int resolved_size = resolved->range_left - resolved->range_right; + if (const_size < resolved_size) { + for (int i = const_size; i < resolved_size; i++) + varbuf->bits.push_back(resolved->is_signed ? varbuf->bits.back() : State::S0); + varbuf->range_left = resolved->range_left; + varbuf->range_right = resolved->range_right; + varbuf->range_swapped = resolved->range_swapped; + varbuf->range_valid = resolved->range_valid; + } } + varbuf = new AstNode(AST_LOCALPARAM, varbuf); + varbuf->str = init_ast->children[0]->str; + AstNode *backup_scope_varbuf = current_scope[varbuf->str]; current_scope[varbuf->str] = varbuf; @@ -1233,7 +1361,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } if (buf->type != AST_CONSTANT) - log_file_error(filename, linenum, "2nd expression of generate for-loop is not constant!\n"); + log_file_error(filename, location.first_line, "2nd expression of generate for-loop is not constant!\n"); if (buf->integer == 0) { delete buf; @@ -1249,7 +1377,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, buf = new AstNode(AST_GENBLOCK, body_ast->clone()); if (buf->str.empty()) { std::stringstream sstr; - sstr << "$genblock$" << filename << ":" << linenum << "$" << (autoidx++); + sstr << "$genblock$" << filename << ":" << location.first_line << "$" << (autoidx++); buf->str = sstr.str(); } std::map<std::string, std::string> name_map; @@ -1279,7 +1407,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } if (buf->type != AST_CONSTANT) - log_file_error(filename, linenum, "Right hand side of 3rd expression of generate for-loop is not constant!\n"); + log_file_error(filename, location.first_line, "Right hand side of 3rd expression of generate for-loop is not constant (%s)!\n", type2str(buf->type).c_str()); delete varbuf->children[0]; varbuf->children[0] = buf; @@ -1303,7 +1431,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, { for (size_t i = 0; i < children.size(); i++) if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF) - log_file_error(children[i]->filename, children[i]->linenum, "Local declaration in unnamed block is an unsupported SystemVerilog feature!\n"); + log_file_error(children[i]->filename, children[i]->location.first_line, "Local declaration in unnamed block is an unsupported SystemVerilog feature!\n"); } // transform block with name @@ -1351,7 +1479,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); - log_file_error(filename, linenum, "Condition for generate if is not constant!\n"); + log_file_error(filename, location.first_line, "Condition for generate if is not constant!\n"); } if (buf->asBool() != 0) { delete buf; @@ -1392,7 +1520,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); - log_file_error(filename, linenum, "Condition for generate case is not constant!\n"); + log_file_error(filename, location.first_line, "Condition for generate case is not constant!\n"); } bool ref_signed = buf->is_signed; @@ -1426,7 +1554,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); - log_file_error(filename, linenum, "Expression in generate case is not constant!\n"); + log_file_error(filename, location.first_line, "Expression in generate case is not constant!\n"); } bool is_selected = RTLIL::const_eq(ref_value, buf->bitsAsConst(), ref_signed && buf->is_signed, ref_signed && buf->is_signed, 1).as_bool(); @@ -1467,7 +1595,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_CELLARRAY) { if (!children.at(0)->range_valid) - log_file_error(filename, linenum, "Non-constant array range on cell array.\n"); + log_file_error(filename, location.first_line, "Non-constant array range on cell array.\n"); newNode = new AstNode(AST_GENBLOCK); int num = max(children.at(0)->range_left, children.at(0)->range_right) - min(children.at(0)->range_left, children.at(0)->range_right) + 1; @@ -1478,7 +1606,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, newNode->children.push_back(new_cell); new_cell->str += stringf("[%d]", idx); if (new_cell->type == AST_PRIMITIVE) { - log_file_error(filename, linenum, "Cell arrays of primitives are currently not supported.\n"); + log_file_error(filename, location.first_line, "Cell arrays of primitives are currently not supported.\n"); } else { log_assert(new_cell->children.at(0)->type == AST_CELLTYPE); new_cell->children.at(0)->str = stringf("$array:%d:%d:%s", i, num, new_cell->children.at(0)->str.c_str()); @@ -1492,7 +1620,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_PRIMITIVE) { if (children.size() < 2) - log_file_error(filename, linenum, "Insufficient number of arguments for primitive `%s'!\n", str.c_str()); + log_file_error(filename, location.first_line, "Insufficient number of arguments for primitive `%s'!\n", str.c_str()); std::vector<AstNode*> children_list; for (auto child : children) { @@ -1507,7 +1635,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1") { if (children_list.size() != 3) - log_file_error(filename, linenum, "Invalid number of arguments for primitive `%s'!\n", str.c_str()); + log_file_error(filename, location.first_line, "Invalid number of arguments for primitive `%s'!\n", str.c_str()); std::vector<RTLIL::State> z_const(1, RTLIL::State::Sz); @@ -1594,18 +1722,19 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, while (left_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); + log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; } did_something = true; newNode = new AstNode(AST_CASE, shift_expr); - for (int i = 0; i <= source_width-result_width; i++) { + for (int i = 0; i < source_width; i++) { int start_bit = children[0]->id2ast->range_right + i; AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit, true)); AstNode *lvalue = children[0]->clone(); lvalue->delete_children(); + int end_bit = std::min(start_bit+result_width,source_width) - 1; lvalue->children.push_back(new AstNode(AST_RANGE, - mkconst_int(start_bit+result_width-1, true), mkconst_int(start_bit, true))); + mkconst_int(end_bit, true), mkconst_int(start_bit, true))); cond->children.push_back(new AstNode(AST_BLOCK, new AstNode(type, lvalue, children[1]->clone()))); newNode->children.push_back(cond); } @@ -1616,7 +1745,7 @@ skip_dynamic_range_lvalue_expansion:; if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && current_block != NULL) { std::stringstream sstr; - sstr << "$formal$" << filename << ":" << linenum << "$" << (autoidx++); + sstr << "$formal$" << filename << ":" << location.first_line << "$" << (autoidx++); std::string id_check = sstr.str() + "_CHECK", id_en = sstr.str() + "_EN"; AstNode *wire_check = new AstNode(AST_WIRE); @@ -1683,6 +1812,7 @@ skip_dynamic_range_lvalue_expansion:; newNode->children.push_back(assign_en); AstNode *assertnode = new AstNode(type); + assertnode->location = location; assertnode->str = str; assertnode->children.push_back(new AstNode(AST_IDENTIFIER)); assertnode->children.push_back(new AstNode(AST_IDENTIFIER)); @@ -1724,10 +1854,10 @@ skip_dynamic_range_lvalue_expansion:; newNode = new AstNode(AST_BLOCK); AstNode *wire_tmp = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(width_hint-1, true), mkconst_int(0, true))); - wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", filename.c_str(), linenum, autoidx++); + wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", filename.c_str(), location.first_line, autoidx++); current_ast_mod->children.push_back(wire_tmp); current_scope[wire_tmp->str] = wire_tmp; - wire_tmp->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire_tmp->attributes[ID::nosync] = AstNode::mkconst_int(1, false); while (wire_tmp->simplify(true, false, false, 1, -1, false, false)) { } wire_tmp->is_logic = true; @@ -1762,13 +1892,16 @@ skip_dynamic_range_lvalue_expansion:; (children[0]->children.size() == 1 || children[0]->children.size() == 2) && children[0]->children[0]->type == AST_RANGE) { std::stringstream sstr; - sstr << "$memwr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++); + sstr << "$memwr$" << children[0]->str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN"; int mem_width, mem_size, addr_bits; bool mem_signed = children[0]->id2ast->is_signed; children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits); + newNode = new AstNode(AST_BLOCK); + AstNode *defNode = new AstNode(AST_BLOCK); + int data_range_left = children[0]->id2ast->children[0]->range_left; int data_range_right = children[0]->id2ast->children[0]->range_right; int mem_data_range_offset = std::min(data_range_left, data_range_right); @@ -1778,31 +1911,6 @@ skip_dynamic_range_lvalue_expansion:; children[0]->children[0]->children[0]->detectSignWidthWorker(addr_width_hint, addr_sign_hint); addr_bits = std::max(addr_bits, addr_width_hint); - AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true))); - wire_addr->str = id_addr; - wire_addr->was_checked = true; - current_ast_mod->children.push_back(wire_addr); - current_scope[wire_addr->str] = wire_addr; - while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } - - AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); - wire_data->str = id_data; - wire_data->was_checked = true; - wire_data->is_signed = mem_signed; - current_ast_mod->children.push_back(wire_data); - current_scope[wire_data->str] = wire_data; - while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } - - AstNode *wire_en = nullptr; - if (current_always->type != AST_INITIAL) { - wire_en = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); - wire_en->str = id_en; - wire_en->was_checked = true; - current_ast_mod->children.push_back(wire_en); - current_scope[wire_en->str] = wire_en; - while (wire_en->simplify(true, false, false, 1, -1, false, false)) { } - } - std::vector<RTLIL::State> x_bits_addr, x_bits_data, set_bits_en; for (int i = 0; i < addr_bits; i++) x_bits_addr.push_back(RTLIL::State::Sx); @@ -1811,32 +1919,79 @@ skip_dynamic_range_lvalue_expansion:; for (int i = 0; i < mem_width; i++) set_bits_en.push_back(RTLIL::State::S1); - AstNode *assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false)); - assign_addr->children[0]->str = id_addr; - assign_addr->children[0]->was_checked = true; + AstNode *node_addr = nullptr; + if (children[0]->children[0]->children[0]->isConst()) { + node_addr = children[0]->children[0]->children[0]->clone(); + } else { + AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true))); + wire_addr->str = id_addr; + wire_addr->was_checked = true; + current_ast_mod->children.push_back(wire_addr); + current_scope[wire_addr->str] = wire_addr; + while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } - AstNode *assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false)); - assign_data->children[0]->str = id_data; - assign_data->children[0]->was_checked = true; + AstNode *assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false)); + assign_addr->children[0]->str = id_addr; + assign_addr->children[0]->was_checked = true; + defNode->children.push_back(assign_addr); - AstNode *assign_en = nullptr; - if (current_always->type != AST_INITIAL) { - assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width)); + assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone()); + assign_addr->children[0]->str = id_addr; + assign_addr->children[0]->was_checked = true; + newNode->children.push_back(assign_addr); + + node_addr = new AstNode(AST_IDENTIFIER); + node_addr->str = id_addr; + } + + AstNode *node_data = nullptr; + if (children[0]->children.size() == 1 && children[1]->isConst()) { + node_data = children[1]->clone(); + } else { + AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); + wire_data->str = id_data; + wire_data->was_checked = true; + wire_data->is_signed = mem_signed; + current_ast_mod->children.push_back(wire_data); + current_scope[wire_data->str] = wire_data; + while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } + + AstNode *assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false)); + assign_data->children[0]->str = id_data; + assign_data->children[0]->was_checked = true; + defNode->children.push_back(assign_data); + + node_data = new AstNode(AST_IDENTIFIER); + node_data->str = id_data; + } + + AstNode *node_en = nullptr; + if (current_always->type == AST_INITIAL) { + node_en = AstNode::mkconst_int(1, false); + } else { + AstNode *wire_en = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); + wire_en->str = id_en; + wire_en->was_checked = true; + current_ast_mod->children.push_back(wire_en); + current_scope[wire_en->str] = wire_en; + while (wire_en->simplify(true, false, false, 1, -1, false, false)) { } + + AstNode *assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width)); assign_en->children[0]->str = id_en; assign_en->children[0]->was_checked = true; - } + defNode->children.push_back(assign_en); - AstNode *default_signals = new AstNode(AST_BLOCK); - default_signals->children.push_back(assign_addr); - default_signals->children.push_back(assign_data); - if (current_always->type != AST_INITIAL) - default_signals->children.push_back(assign_en); - current_top_block->children.insert(current_top_block->children.begin(), default_signals); + node_en = new AstNode(AST_IDENTIFIER); + node_en->str = id_en; + } - assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone()); - assign_addr->children[0]->str = id_addr; - assign_addr->children[0]->was_checked = true; + if (!defNode->children.empty()) + current_top_block->children.insert(current_top_block->children.begin(), defNode); + else + delete defNode; + AstNode *assign_data = nullptr; + AstNode *assign_en = nullptr; if (children[0]->children.size() == 2) { if (children[0]->children[1]->range_valid) @@ -1873,7 +2028,7 @@ skip_dynamic_range_lvalue_expansion:; while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); + log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), @@ -1897,9 +2052,11 @@ skip_dynamic_range_lvalue_expansion:; } else { - assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[1]->clone()); - assign_data->children[0]->str = id_data; - assign_data->children[0]->was_checked = true; + if (!(children[0]->children.size() == 1 && children[1]->isConst())) { + assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[1]->clone()); + assign_data->children[0]->str = id_data; + assign_data->children[0]->was_checked = true; + } if (current_always->type != AST_INITIAL) { assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false)); @@ -1907,28 +2064,20 @@ skip_dynamic_range_lvalue_expansion:; assign_en->children[0]->was_checked = true; } } - - newNode = new AstNode(AST_BLOCK); - newNode->children.push_back(assign_addr); - newNode->children.push_back(assign_data); - if (current_always->type != AST_INITIAL) + if (assign_data) + newNode->children.push_back(assign_data); + if (assign_en) newNode->children.push_back(assign_en); - AstNode *wrnode = new AstNode(current_always->type == AST_INITIAL ? AST_MEMINIT : AST_MEMWR); - wrnode->children.push_back(new AstNode(AST_IDENTIFIER)); - wrnode->children.push_back(new AstNode(AST_IDENTIFIER)); - if (current_always->type != AST_INITIAL) - wrnode->children.push_back(new AstNode(AST_IDENTIFIER)); - else - wrnode->children.push_back(AstNode::mkconst_int(1, false)); + AstNode *wrnode = new AstNode(current_always->type == AST_INITIAL ? AST_MEMINIT : AST_MEMWR, node_addr, node_data, node_en); wrnode->str = children[0]->str; wrnode->id2ast = children[0]->id2ast; - wrnode->children[0]->str = id_addr; - wrnode->children[1]->str = id_data; - if (current_always->type != AST_INITIAL) - wrnode->children[2]->str = id_en; current_ast_mod->children.push_back(wrnode); + if (newNode->children.empty()) { + delete newNode; + newNode = new AstNode(); + } goto apply_newNode; } @@ -1969,11 +2118,11 @@ skip_dynamic_range_lvalue_expansion:; int num_steps = 1; if (GetSize(children) != 1 && GetSize(children) != 2) - log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 2.\n", + log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1 or 2.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); if (!current_always_clocked) - log_file_error(filename, linenum, "System function %s is only allowed in clocked blocks.\n", + log_file_error(filename, location.first_line, "System function %s is only allowed in clocked blocks.\n", RTLIL::unescape_id(str).c_str()); if (GetSize(children) == 2) @@ -1981,7 +2130,7 @@ skip_dynamic_range_lvalue_expansion:; AstNode *buf = children[1]->clone(); while (buf->simplify(true, false, false, stage, -1, false, false)) { } if (buf->type != AST_CONSTANT) - log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); num_steps = buf->asInt(true); delete buf; @@ -2008,7 +2157,7 @@ skip_dynamic_range_lvalue_expansion:; AstNode *reg = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(width_hint-1, true), mkconst_int(0, true))); - reg->str = stringf("$past$%s:%d$%d$%d", filename.c_str(), linenum, myidx, i); + reg->str = stringf("$past$%s:%d$%d$%d", filename.c_str(), location.first_line, myidx, i); reg->is_reg = true; current_ast_mod->children.push_back(reg); @@ -2043,11 +2192,11 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell" || str == "\\$changed") { if (GetSize(children) != 1) - log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", + log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); if (!current_always_clocked) - log_file_error(filename, linenum, "System function %s is only allowed in clocked blocks.\n", + log_file_error(filename, location.first_line, "System function %s is only allowed in clocked blocks.\n", RTLIL::unescape_id(str).c_str()); AstNode *present = children.at(0)->clone(); @@ -2085,13 +2234,13 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$clog2") { if (children.size() != 1) - log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", + log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); AstNode *buf = children[0]->clone(); while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (buf->type != AST_CONSTANT) - log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); RTLIL::Const arg_value = buf->bitsAsConst(); if (arg_value.as_bool()) @@ -2110,11 +2259,11 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$size" || str == "\\$bits") { if (str == "\\$bits" && children.size() != 1) - log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", + log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); if (str == "\\$size" && children.size() != 1 && children.size() != 2) - log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 2.\n", + log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1 or 2.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); int dim = 1; @@ -2138,7 +2287,7 @@ skip_dynamic_range_lvalue_expansion:; if (id_ast == NULL && current_scope.count(buf->str)) id_ast = current_scope.at(buf->str); if (!id_ast) - log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", buf->str.c_str()); + log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", buf->str.c_str()); if (id_ast->type == AST_MEMORY) { // We got here only if the argument is a memory // Otherwise $size() and $bits() return the expression width @@ -2146,15 +2295,15 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$bits") { if (mem_range->type == AST_RANGE) { if (!mem_range->range_valid) - log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", buf->str.c_str()); + log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", buf->str.c_str()); mem_depth = mem_range->range_left - mem_range->range_right + 1; } else - log_file_error(filename, linenum, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str()); + log_file_error(filename, location.first_line, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str()); } else { // $size() if (mem_range->type == AST_RANGE) { if (!mem_range->range_valid) - log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", buf->str.c_str()); + log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", buf->str.c_str()); int dims; if (id_ast->multirange_dimensions.empty()) dims = 1; @@ -2165,9 +2314,9 @@ skip_dynamic_range_lvalue_expansion:; else if (dim <= dims) { width_hint = id_ast->multirange_dimensions[2*dim-1]; } else if ((dim > dims+1) || (dim < 0)) - log_file_error(filename, linenum, "Dimension %d out of range in `%s', as it only has dimensions 1..%d!\n", dim, buf->str.c_str(), dims+1); + log_file_error(filename, location.first_line, "Dimension %d out of range in `%s', as it only has dimensions 1..%d!\n", dim, buf->str.c_str(), dims+1); } else - log_file_error(filename, linenum, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str()); + log_file_error(filename, location.first_line, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str()); } } } @@ -2188,18 +2337,18 @@ skip_dynamic_range_lvalue_expansion:; if (func_with_two_arguments) { if (children.size() != 2) - log_file_error(filename, linenum, "System function %s got %d arguments, expected 2.\n", + log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 2.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); } else { if (children.size() != 1) - log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", + log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); } if (children.size() >= 1) { while (children[0]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (!children[0]->isConst()) - log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant argument.\n", + log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant argument.\n", RTLIL::unescape_id(str).c_str()); int child_width_hint = width_hint; bool child_sign_hint = sign_hint; @@ -2210,7 +2359,7 @@ skip_dynamic_range_lvalue_expansion:; if (children.size() >= 2) { while (children[1]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (!children[1]->isConst()) - log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant argument.\n", + log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant argument.\n", RTLIL::unescape_id(str).c_str()); int child_width_hint = width_hint; bool child_sign_hint = sign_hint; @@ -2253,7 +2402,7 @@ skip_dynamic_range_lvalue_expansion:; AstNode *node_string = children[0]; while (node_string->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (node_string->type != AST_CONSTANT) - log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str()); std::string sformat = node_string->bitsAsConst().decode_string(); std::string sout = process_format_str(sformat, 1, stage, width_hint, sign_hint); newNode = AstNode::mkconst_str(sout); @@ -2274,14 +2423,14 @@ skip_dynamic_range_lvalue_expansion:; for (int i = 2; i < GetSize(dpi_decl->children); i++) { if (i-2 >= GetSize(children)) - log_file_error(filename, linenum, "Insufficient number of arguments in DPI function call.\n"); + log_file_error(filename, location.first_line, "Insufficient number of arguments in DPI function call.\n"); argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str)); args.push_back(children.at(i-2)->clone()); while (args.back()->simplify(true, false, false, stage, -1, false, true)) { } if (args.back()->type != AST_CONSTANT && args.back()->type != AST_REALVALUE) - log_file_error(filename, linenum, "Failed to evaluate DPI function with non-constant argument.\n"); + log_file_error(filename, location.first_line, "Failed to evaluate DPI function with non-constant argument.\n"); } newNode = dpi_call(rtype, fname, argtypes, args); @@ -2293,7 +2442,7 @@ skip_dynamic_range_lvalue_expansion:; } if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION) - log_file_error(filename, linenum, "Can't resolve function name `%s'.\n", str.c_str()); + log_file_error(filename, location.first_line, "Can't resolve function name `%s'.\n", str.c_str()); } if (type == AST_TCALL) @@ -2301,26 +2450,26 @@ skip_dynamic_range_lvalue_expansion:; if (str == "$finish" || str == "$stop") { if (!current_always || current_always->type != AST_INITIAL) - log_file_error(filename, linenum, "System task `%s' outside initial block is unsupported.\n", str.c_str()); + log_file_error(filename, location.first_line, "System task `%s' outside initial block is unsupported.\n", str.c_str()); - log_file_error(filename, linenum, "System task `%s' executed.\n", str.c_str()); + log_file_error(filename, location.first_line, "System task `%s' executed.\n", str.c_str()); } if (str == "\\$readmemh" || str == "\\$readmemb") { if (GetSize(children) < 2 || GetSize(children) > 4) - log_file_error(filename, linenum, "System function %s got %d arguments, expected 2-4.\n", + log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 2-4.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); AstNode *node_filename = children[0]->clone(); while (node_filename->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (node_filename->type != AST_CONSTANT) - log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str()); AstNode *node_memory = children[1]->clone(); while (node_memory->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY) - log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str()); int start_addr = -1, finish_addr = -1; @@ -2328,7 +2477,7 @@ skip_dynamic_range_lvalue_expansion:; AstNode *node_addr = children[2]->clone(); while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (node_addr->type != AST_CONSTANT) - log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str()); start_addr = int(node_addr->asInt(false)); } @@ -2336,7 +2485,7 @@ skip_dynamic_range_lvalue_expansion:; AstNode *node_addr = children[3]->clone(); while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (node_addr->type != AST_CONSTANT) - log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str()); + log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str()); finish_addr = int(node_addr->asInt(false)); } @@ -2364,13 +2513,13 @@ skip_dynamic_range_lvalue_expansion:; } if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK) - log_file_error(filename, linenum, "Can't resolve task name `%s'.\n", str.c_str()); + log_file_error(filename, location.first_line, "Can't resolve task name `%s'.\n", str.c_str()); } AstNode *decl = current_scope[str]; std::stringstream sstr; - sstr << "$func$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++) << "$"; + sstr << "$func$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++) << "$"; std::string prefix = sstr.str(); bool recommend_const_eval = false; @@ -2392,9 +2541,9 @@ skip_dynamic_range_lvalue_expansion:; } if (in_param) - log_file_error(filename, linenum, "Non-constant function call in constant expression.\n"); + log_file_error(filename, location.first_line, "Non-constant function call in constant expression.\n"); if (require_const_eval) - log_file_error(filename, linenum, "Function %s can only be called with constant arguments.\n", str.c_str()); + log_file_error(filename, location.first_line, "Function %s can only be called with constant arguments.\n", str.c_str()); } size_t arg_count = 0; @@ -2498,7 +2647,7 @@ skip_dynamic_range_lvalue_expansion:; } for (auto child : decl->children) - if (child->type == AST_WIRE || child->type == AST_MEMORY || child->type == AST_PARAMETER || child->type == AST_LOCALPARAM) + if (child->type == AST_WIRE || child->type == AST_MEMORY || child->type == AST_PARAMETER || child->type == AST_LOCALPARAM || child->type == AST_ENUM_ITEM) { AstNode *wire = nullptr; @@ -2516,7 +2665,7 @@ skip_dynamic_range_lvalue_expansion:; goto tcall_incompatible_wires; } else { tcall_incompatible_wires: - log_file_error(filename, linenum, "Incompatible re-declaration of wire %s.\n", child->str.c_str()); + log_file_error(filename, location.first_line, "Incompatible re-declaration of wire %s.\n", child->str.c_str()); } } } @@ -2528,7 +2677,10 @@ skip_dynamic_range_lvalue_expansion:; wire->is_input = false; wire->is_output = false; wire->is_reg = true; - wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + if (child->type == AST_ENUM_ITEM) + wire->attributes["\\enum_base_type"] = child->attributes["\\enum_base_type"]; + wire_cache[child->str] = wire; current_ast_mod->children.push_back(wire); @@ -2604,7 +2756,7 @@ replace_fcall_later:; switch (type) { case AST_IDENTIFIER: - if (current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM)) { + if (current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM || current_scope[str]->type == AST_ENUM_ITEM)) { if (current_scope[str]->children[0]->type == AST_CONSTANT) { if (children.size() != 0 && children[0]->type == AST_RANGE && children[0]->range_valid) { std::vector<RTLIL::State> data; @@ -2867,7 +3019,7 @@ apply_newNode: // newNode->dumpAst(stderr, "+ "); log_assert(newNode != NULL); newNode->filename = filename; - newNode->linenum = linenum; + newNode->location = location; newNode->cloneInto(this); delete newNode; did_something = true; @@ -2903,10 +3055,20 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m std::ifstream f; f.open(mem_filename.c_str()); - yosys_input_files.insert(mem_filename); - - if (f.fail()) - log_file_error(filename, linenum, "Can not open file `%s` for %s.\n", mem_filename.c_str(), str.c_str()); + if (f.fail()) { +#ifdef _WIN32 + char slash = '\\'; +#else + char slash = '/'; +#endif + std::string path = filename.substr(0, filename.find_last_of(slash)+1); + f.open(path + mem_filename.c_str()); + yosys_input_files.insert(path + mem_filename); + } else { + yosys_input_files.insert(mem_filename); + } + if (f.fail() || GetSize(mem_filename) == 0) + log_file_error(filename, location.first_line, "Can not open file `%s` for %s.\n", mem_filename.c_str(), str.c_str()); log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid); int range_left = memory->children[1]->range_left, range_right = memory->children[1]->range_right; @@ -2952,7 +3114,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m char *endptr; cursor = strtol(nptr, &endptr, 16); if (!*nptr || *endptr) - log_file_error(filename, linenum, "Can not parse address `%s` for %s.\n", nptr, str.c_str()); + log_file_error(filename, location.first_line, "Can not parse address `%s` for %s.\n", nptr, str.c_str()); continue; } @@ -3022,14 +3184,6 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma current_ast_mod->children.push_back(p); str = p->str; id2ast = p; - - auto resolved = current_scope.at(index_var); - if (resolved->range_valid) { - p->range_left = resolved->range_left; - p->range_right = resolved->range_right; - p->range_swapped = resolved->range_swapped; - p->range_valid = resolved->range_valid; - } } } @@ -3041,7 +3195,7 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma for (size_t i = 0; i < children.size(); i++) { AstNode *child = children[i]; if (child->type == AST_WIRE || child->type == AST_MEMORY || child->type == AST_PARAMETER || child->type == AST_LOCALPARAM || - child->type == AST_FUNCTION || child->type == AST_TASK || child->type == AST_CELL || child->type == AST_TYPEDEF) { + child->type == AST_FUNCTION || child->type == AST_TASK || child->type == AST_CELL || child->type == AST_TYPEDEF || child->type == AST_ENUM_ITEM) { if (backup_name_map.size() == 0) backup_name_map = name_map; std::string new_name = prefix[0] == '\\' ? prefix.substr(1) : prefix; @@ -3060,6 +3214,27 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma child->str = new_name; current_scope[new_name] = child; } + if (child->type == AST_ENUM){ + current_scope[child->str] = child; + for (auto enode : child->children){ + log_assert(enode->type == AST_ENUM_ITEM); + if (backup_name_map.size() == 0) + backup_name_map = name_map; + std::string new_name = prefix[0] == '\\' ? prefix.substr(1) : prefix; + size_t pos = enode->str.rfind('.'); + if (pos == std::string::npos) + pos = enode->str[0] == '\\' && prefix[0] == '\\' ? 1 : 0; + else + pos = pos + 1; + new_name = enode->str.substr(0, pos) + new_name + enode->str.substr(pos); + if (new_name[0] != '$' && new_name[0] != '\\') + new_name = prefix[0] + new_name; + name_map[enode->str] = new_name; + + enode->str = new_name; + current_scope[new_name] = enode; + } + } } for (size_t i = 0; i < children.size(); i++) { @@ -3114,7 +3289,7 @@ static void mark_memories_assign_lhs_complex(dict<AstNode*, pool<std::string>> & if (that->type == AST_IDENTIFIER && that->id2ast && that->id2ast->type == AST_MEMORY) { AstNode *mem = that->id2ast; if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_CMPLX_LHS)) - mem2reg_places[mem].insert(stringf("%s:%d", that->filename.c_str(), that->linenum)); + mem2reg_places[mem].insert(stringf("%s:%d", that->filename.c_str(), that->location.first_line)); mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CMPLX_LHS; } } @@ -3142,14 +3317,14 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg // activate mem2reg if this is assigned in an async proc if (flags & AstNode::MEM2REG_FL_ASYNC) { if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ASYNC)) - mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), linenum)); + mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line)); mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ASYNC; } // remember if this is assigned blocking (=) if (type == AST_ASSIGN_EQ) { if (!(proc_flags[mem] & AstNode::MEM2REG_FL_EQ1)) - mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), linenum)); + mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line)); proc_flags[mem] |= AstNode::MEM2REG_FL_EQ1; } @@ -3166,11 +3341,11 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg // remember where this is if (flags & MEM2REG_FL_INIT) { if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_INIT)) - mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), linenum)); + mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line)); mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_INIT; } else { if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ELSE)) - mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), linenum)); + mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line)); mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ELSE; } } @@ -3184,16 +3359,16 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg // flag if used after blocking assignment (in same proc) if ((proc_flags[mem] & AstNode::MEM2REG_FL_EQ1) && !(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_EQ2)) { - mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), linenum)); + mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line)); mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_EQ2; } } // also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg' - if (type == AST_MEMORY && (get_bool_attribute("\\mem2reg") || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg)) + if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg)) mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED; - if (type == AST_MODULE && get_bool_attribute("\\mem2reg")) + if (type == AST_MODULE && get_bool_attribute(ID::mem2reg)) children_flags |= AstNode::MEM2REG_FL_ALL; dict<AstNode*, uint32_t> *proc_flags_p = NULL; @@ -3253,7 +3428,7 @@ bool AstNode::mem2reg_check(pool<AstNode*> &mem2reg_set) return false; if (children.empty() || children[0]->type != AST_RANGE || GetSize(children[0]->children) != 1) - log_file_error(filename, linenum, "Invalid array access.\n"); + log_file_error(filename, location.first_line, "Invalid array access.\n"); return true; } @@ -3345,7 +3520,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, children[0]->children[0]->children[0]->type != AST_CONSTANT) { std::stringstream sstr; - sstr << "$mem2reg_wr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++); + sstr << "$mem2reg_wr$" << children[0]->str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA"; int mem_width, mem_size, addr_bits; @@ -3356,7 +3531,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, wire_addr->str = id_addr; wire_addr->is_reg = true; wire_addr->was_checked = true; - wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false); mod->children.push_back(wire_addr); while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } @@ -3365,7 +3540,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, wire_data->is_reg = true; wire_data->was_checked = true; wire_data->is_signed = mem_signed; - wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); mod->children.push_back(wire_data); while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } @@ -3424,7 +3599,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, else { std::stringstream sstr; - sstr << "$mem2reg_rd$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++); + sstr << "$mem2reg_rd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA"; int mem_width, mem_size, addr_bits; @@ -3436,7 +3611,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, wire_addr->is_reg = true; wire_addr->was_checked = true; if (block) - wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false); mod->children.push_back(wire_addr); while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } @@ -3446,7 +3621,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, wire_data->was_checked = true; wire_data->is_signed = mem_signed; if (block) - wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); mod->children.push_back(wire_data); while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } @@ -3568,13 +3743,13 @@ void AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &varia int offset = variables.at(str).offset, width = variables.at(str).val.bits.size(); if (!children.empty()) { if (children.size() != 1 || children.at(0)->type != AST_RANGE) - log_file_error(filename, linenum, "Memory access in constant function is not supported\n%s:%d: ...called from here.\n", - fcall->filename.c_str(), fcall->linenum); + log_file_error(filename, location.first_line, "Memory access in constant function is not supported\n%s:%d.%d-%d.%d: ...called from here.\n", + fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); children.at(0)->replace_variables(variables, fcall); while (simplify(true, false, false, 1, -1, false, true)) { } if (!children.at(0)->range_valid) - log_file_error(filename, linenum, "Non-constant range\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + log_file_error(filename, location.first_line, "Non-constant range\n%s:%d.%d-%d.%d: ... called from here.\n", + fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); offset = min(children.at(0)->range_left, children.at(0)->range_right); width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width); } @@ -3605,8 +3780,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) { while (child->simplify(true, false, false, 1, -1, false, true)) { } if (!child->range_valid) - log_file_error(child->filename, child->linenum, "Can't determine size of variable %s\n%s:%d: ... called from here.\n", - child->str.c_str(), fcall->filename.c_str(), fcall->linenum); + log_file_error(child->filename, child->location.first_line, "Can't determine size of variable %s\n%s:%d.%d-%d.%d: ... called from here.\n", + child->str.c_str(), fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); variables[child->str].val = RTLIL::Const(RTLIL::State::Sx, abs(child->range_left - child->range_right)+1); variables[child->str].offset = min(child->range_left, child->range_right); variables[child->str].is_signed = child->is_signed; @@ -3645,24 +3820,24 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) continue; if (stmt->children.at(1)->type != AST_CONSTANT) - log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here. X\n", - fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s:%d.%d-%d.%d: ... called from here. X\n", + fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); if (stmt->children.at(0)->type != AST_IDENTIFIER) - log_file_error(stmt->filename, stmt->linenum, "Unsupported composite left hand side in constant function\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->location.first_line, "Unsupported composite left hand side in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", + fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); if (!variables.count(stmt->children.at(0)->str)) - log_file_error(stmt->filename, stmt->linenum, "Assignment to non-local variable in constant function\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->location.first_line, "Assignment to non-local variable in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", + fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); if (stmt->children.at(0)->children.empty()) { variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size()); } else { AstNode *range = stmt->children.at(0)->children.at(0); if (!range->range_valid) - log_file_error(range->filename, range->linenum, "Non-constant range\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + log_file_error(range->filename, range->location.first_line, "Non-constant range\n%s:%d.%d-%d.%d: ... called from here.\n", + fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); int offset = min(range->range_left, range->range_right); int width = std::abs(range->range_left - range->range_right) + 1; varinfo_t &v = variables[stmt->children.at(0)->str]; @@ -3693,8 +3868,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) while (cond->simplify(true, false, false, 1, -1, false, true)) { } if (cond->type != AST_CONSTANT) - log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", + fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); if (cond->asBool()) { block->children.insert(block->children.begin(), stmt->children.at(1)->clone()); @@ -3714,8 +3889,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) while (num->simplify(true, false, false, 1, -1, false, true)) { } if (num->type != AST_CONSTANT) - log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", + fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); block->children.erase(block->children.begin()); for (int i = 0; i < num->bitsAsConst().as_int(); i++) @@ -3752,8 +3927,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) while (cond->simplify(true, false, false, 1, -1, false, true)) { } if (cond->type != AST_CONSTANT) - log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", + fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); found_match = cond->asBool(); delete cond; @@ -3782,8 +3957,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) continue; } - log_file_error(stmt->filename, stmt->linenum, "Unsupported language construct in constant function\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->location.first_line, "Unsupported language construct in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", + fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); log_abort(); } @@ -3798,4 +3973,32 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) return AstNode::mkconst_bits(variables.at(str).val.bits, variables.at(str).is_signed); } +void AstNode::allocateDefaultEnumValues() +{ + log_assert(type==AST_ENUM); + int last_enum_int = -1; + for (auto node : children) { + log_assert(node->type==AST_ENUM_ITEM); + node->attributes["\\enum_base_type"] = mkconst_str(str); + for (size_t i = 0; i < node->children.size(); i++) { + switch (node->children[i]->type) { + case AST_NONE: + // replace with auto-incremented constant + delete node->children[i]; + node->children[i] = AstNode::mkconst_int(++last_enum_int, true); + break; + case AST_CONSTANT: + // explicit constant (or folded expression) + // TODO: can't extend 'x or 'z item + last_enum_int = node->children[i]->integer; + break; + default: + // ignore ranges + break; + } + // TODO: range check + } + } +} + YOSYS_NAMESPACE_END |