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-rw-r--r--frontends/ast/genrtlil.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index f7e7b852c..1453d13a9 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -265,6 +265,7 @@ struct AST_INTERNAL::ProcessGenerator
{
// generate process and simple root case
proc = new RTLIL::Process;
+ proc->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, RTLIL::autoidx++);
for (auto &attr : always->attributes) {
if (attr.second->type != AST_CONSTANT)
@@ -360,6 +361,8 @@ struct AST_INTERNAL::ProcessGenerator
do {
wire->name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
+ if (chunk.wire->name.find('$') != std::string::npos)
+ wire->name += stringf("$%d", RTLIL::autoidx++);
} while (current_module->wires.count(wire->name) > 0);
wire->width = chunk.width;
current_module->wires[wire->name] = wire;