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-rw-r--r--frontends/ilang/ilang_parser.y11
1 files changed, 7 insertions, 4 deletions
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index 4e0b62edd..0522fa72a 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -169,7 +169,7 @@ wire_stmt:
current_wire->attributes = attrbuf;
attrbuf.clear();
} wire_options TOK_ID EOL {
- if (current_module->wires_.count($4) != 0)
+ if (current_module->wire($4) != nullptr)
rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of wire %s.", $4).c_str());
current_module->rename(current_wire, $4);
free($4);
@@ -179,6 +179,9 @@ wire_options:
wire_options TOK_WIDTH TOK_INT {
current_wire->width = $3;
} |
+ wire_options TOK_WIDTH TOK_INVALID {
+ rtlil_frontend_ilang_yyerror("ilang error: invalid wire width");
+ } |
wire_options TOK_UPTO {
current_wire->upto = true;
} |
@@ -229,7 +232,7 @@ memory_options:
cell_stmt:
TOK_CELL TOK_ID TOK_ID EOL {
- if (current_module->cells_.count($3) != 0)
+ if (current_module->cell($3) != nullptr)
rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell %s.", $3).c_str());
current_cell = current_module->addCell($3, $2);
current_cell->attributes = attrbuf;
@@ -424,9 +427,9 @@ sigspec:
delete $1;
} |
TOK_ID {
- if (current_module->wires_.count($1) == 0)
+ if (current_module->wire($1) == nullptr)
rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
- $$ = new RTLIL::SigSpec(current_module->wires_[$1]);
+ $$ = new RTLIL::SigSpec(current_module->wire($1));
free($1);
} |
sigspec '[' TOK_INT ']' {