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-rw-r--r--frontends/liberty/liberty.cc152
1 files changed, 76 insertions, 76 deletions
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 14de95e07..6f0c3fefa 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -55,37 +55,37 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
- cell->setPort("\\A", A);
- cell->setPort("\\Y", module->addWire(NEW_ID));
- return cell->getPort("\\Y");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
+ cell->setPort(ID::A, A);
+ cell->setPort(ID::Y, module->addWire(NEW_ID));
+ return cell->getPort(ID::Y);
}
static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_XOR_");
- cell->setPort("\\A", A);
- cell->setPort("\\B", B);
- cell->setPort("\\Y", module->addWire(NEW_ID));
- return cell->getPort("\\Y");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_XOR_));
+ cell->setPort(ID::A, A);
+ cell->setPort(ID::B, B);
+ cell->setPort(ID::Y, module->addWire(NEW_ID));
+ return cell->getPort(ID::Y);
}
static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_AND_");
- cell->setPort("\\A", A);
- cell->setPort("\\B", B);
- cell->setPort("\\Y", module->addWire(NEW_ID));
- return cell->getPort("\\Y");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_AND_));
+ cell->setPort(ID::A, A);
+ cell->setPort(ID::B, B);
+ cell->setPort(ID::Y, module->addWire(NEW_ID));
+ return cell->getPort(ID::Y);
}
static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_OR_");
- cell->setPort("\\A", A);
- cell->setPort("\\B", B);
- cell->setPort("\\Y", module->addWire(NEW_ID));
- return cell->getPort("\\Y");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_OR_));
+ cell->setPort(ID::A, A);
+ cell->setPort(ID::B, B);
+ cell->setPort(ID::Y, module->addWire(NEW_ID));
+ return cell->getPort(ID::Y);
}
static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack, token_t next_token)
@@ -241,32 +241,32 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
- if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clk_sig) {
- clk_sig = it.second->getPort("\\A");
+ if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clk_sig) {
+ clk_sig = it.second->getPort(ID::A);
clk_polarity = !clk_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
- clear_sig = it.second->getPort("\\A");
+ if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
+ clear_sig = it.second->getPort(ID::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
- preset_sig = it.second->getPort("\\A");
+ if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
+ preset_sig = it.second->getPort(ID::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
}
}
}
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
- cell->setPort("\\A", iq_sig);
- cell->setPort("\\Y", iqn_sig);
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
+ cell->setPort(ID::A, iq_sig);
+ cell->setPort(ID::Y, iqn_sig);
cell = module->addCell(NEW_ID, "");
- cell->setPort("\\D", data_sig);
- cell->setPort("\\Q", iq_sig);
- cell->setPort("\\C", clk_sig);
+ cell->setPort(ID::D, data_sig);
+ cell->setPort(ID::Q, iq_sig);
+ cell->setPort(ID::C, clk_sig);
if (clear_sig.size() == 0 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
@@ -274,18 +274,18 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
if (clear_sig.size() == 1 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
- cell->setPort("\\R", clear_sig);
+ cell->setPort(ID::R, clear_sig);
}
if (clear_sig.size() == 0 && preset_sig.size() == 1) {
cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
- cell->setPort("\\R", preset_sig);
+ cell->setPort(ID::R, preset_sig);
}
if (clear_sig.size() == 1 && preset_sig.size() == 1) {
cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
- cell->setPort("\\S", preset_sig);
- cell->setPort("\\R", clear_sig);
+ cell->setPort(ID::S, preset_sig);
+ cell->setPort(ID::R, clear_sig);
}
log_assert(!cell->type.empty());
@@ -324,27 +324,27 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
- if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == enable_sig) {
- enable_sig = it.second->getPort("\\A");
+ if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == enable_sig) {
+ enable_sig = it.second->getPort(ID::A);
enable_polarity = !enable_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
- clear_sig = it.second->getPort("\\A");
+ if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
+ clear_sig = it.second->getPort(ID::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
- preset_sig = it.second->getPort("\\A");
+ if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
+ preset_sig = it.second->getPort(ID::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
}
}
}
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
- cell->setPort("\\A", iq_sig);
- cell->setPort("\\Y", iqn_sig);
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
+ cell->setPort(ID::A, iq_sig);
+ cell->setPort(ID::Y, iqn_sig);
if (clear_sig.size() == 1)
{
@@ -353,25 +353,25 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
if (clear_polarity == true || clear_polarity != enable_polarity)
{
- RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
- inv->setPort("\\A", clear_sig);
- inv->setPort("\\Y", module->addWire(NEW_ID));
+ RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
+ inv->setPort(ID::A, clear_sig);
+ inv->setPort(ID::Y, module->addWire(NEW_ID));
if (clear_polarity == true)
- clear_negative = inv->getPort("\\Y");
+ clear_negative = inv->getPort(ID::Y);
if (clear_polarity != enable_polarity)
- clear_enable = inv->getPort("\\Y");
+ clear_enable = inv->getPort(ID::Y);
}
- RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_AND_");
- data_gate->setPort("\\A", data_sig);
- data_gate->setPort("\\B", clear_negative);
- data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
+ RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_));
+ data_gate->setPort(ID::A, data_sig);
+ data_gate->setPort(ID::B, clear_negative);
+ data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
- RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
- enable_gate->setPort("\\A", enable_sig);
- enable_gate->setPort("\\B", clear_enable);
- enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
+ RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
+ enable_gate->setPort(ID::A, enable_sig);
+ enable_gate->setPort(ID::B, clear_enable);
+ enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
}
if (preset_sig.size() == 1)
@@ -381,31 +381,31 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
if (preset_polarity == false || preset_polarity != enable_polarity)
{
- RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
- inv->setPort("\\A", preset_sig);
- inv->setPort("\\Y", module->addWire(NEW_ID));
+ RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
+ inv->setPort(ID::A, preset_sig);
+ inv->setPort(ID::Y, module->addWire(NEW_ID));
if (preset_polarity == false)
- preset_positive = inv->getPort("\\Y");
+ preset_positive = inv->getPort(ID::Y);
if (preset_polarity != enable_polarity)
- preset_enable = inv->getPort("\\Y");
+ preset_enable = inv->getPort(ID::Y);
}
- RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_OR_");
- data_gate->setPort("\\A", data_sig);
- data_gate->setPort("\\B", preset_positive);
- data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
+ RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_));
+ data_gate->setPort(ID::A, data_sig);
+ data_gate->setPort(ID::B, preset_positive);
+ data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
- RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
- enable_gate->setPort("\\A", enable_sig);
- enable_gate->setPort("\\B", preset_enable);
- enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
+ RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
+ enable_gate->setPort(ID::A, enable_sig);
+ enable_gate->setPort(ID::B, preset_enable);
+ enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
}
cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
- cell->setPort("\\D", data_sig);
- cell->setPort("\\Q", iq_sig);
- cell->setPort("\\E", enable_sig);
+ cell->setPort(ID::D, data_sig);
+ cell->setPort(ID::Q, iq_sig);
+ cell->setPort(ID::E, enable_sig);
return true;
}
@@ -550,13 +550,13 @@ struct LibertyFrontend : public Frontend {
if (design->has(cell_name)) {
Module *existing_mod = design->module(cell_name);
- if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
+ if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) {
log_error("Re-definition of cell/module %s!\n", log_id(cell_name));
} else if (flag_nooverwrite) {
log("Ignoring re-definition of module %s.\n", log_id(cell_name));
continue;
} else {
- log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", log_id(cell_name));
+ log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", log_id(cell_name));
design->remove(existing_mod);
}
}
@@ -570,7 +570,7 @@ struct LibertyFrontend : public Frontend {
module->name = cell_name;
if (flag_lib)
- module->set_bool_attribute("\\blackbox");
+ module->set_bool_attribute(ID::blackbox);
for (auto &attr : attributes)
module->attributes[attr] = 1;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 16:07:28 +0000