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-rw-r--r--frontends/verific/verific.cc90
1 files changed, 62 insertions, 28 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index cb0368fd5..632dc51fd 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -48,12 +48,13 @@ USING_YOSYS_NAMESPACE
#include "VeriWrite.h"
#include "VhdlUnits.h"
#include "VeriLibrary.h"
+#include "VeriExtensions.h"
#ifndef SYMBIOTIC_VERIFIC_API_VERSION
# error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific."
#endif
-#if SYMBIOTIC_VERIFIC_API_VERSION < 1
+#if SYMBIOTIC_VERIFIC_API_VERSION < 202006
# error "Please update your version of Symbiotic EDA flavored Verific."
#endif
@@ -1109,7 +1110,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex());
- import_attributes(wire->attributes, netbus, nl);
+ MapIter mibus;
+ FOREACH_NET_OF_NETBUS(netbus, mibus, net) {
+ if (net)
+ import_attributes(wire->attributes, net, nl);
+ break;
+ }
RTLIL::Const initval = Const(State::Sx, GetSize(wire));
bool initval_valid = false;
@@ -1262,7 +1268,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
if (inst->Type() == OPER_READ_PORT)
{
- RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetInput()->Name()));
+ RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetInput()->Name()), nullptr);
+ if (!memory)
+ log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst->GetInput()->Name());
+
int numchunks = int(inst->OutputSize()) / memory->width;
int chunksbits = ceil_log2(numchunks);
@@ -1289,7 +1298,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
if (inst->Type() == OPER_WRITE_PORT || inst->Type() == OPER_CLOCKED_WRITE_PORT)
{
- RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()));
+ RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()), nullptr);
+ if (!memory)
+ log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst->GetInput()->Name());
int numchunks = int(inst->Input2Size()) / memory->width;
int chunksbits = ceil_log2(numchunks);
@@ -1435,6 +1446,16 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
continue;
}
+ if (inst->Type() == PRIM_SEDA_INITSTATE)
+ {
+ SigBit initstate = module->Initstate(new_verific_id(inst));
+ SigBit sig_o = net_map_at(inst->GetOutput());
+ module->connect(sig_o, initstate);
+
+ if (!mode_keep)
+ continue;
+ }
+
if (!mode_keep && verific_sva_prims.count(inst->Type())) {
if (verific_verbose)
log(" skipping SVA cell in non k-mode\n");
@@ -1877,7 +1898,7 @@ struct VerificExtNets
new_net = new Net(name.c_str());
nl->Add(new_net);
- Net *n YS_ATTRIBUTE(unused) = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
+ Net *n = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
log_assert(n == ca_net);
}
@@ -1912,6 +1933,9 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
for (const auto &i : parameters)
verific_params.Insert(i.first.c_str(), i.second.c_str());
+ InitialAssertionRewriter rw;
+ rw.RegisterCallBack();
+
if (top.empty()) {
netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
}
@@ -2003,7 +2027,7 @@ bool check_noverific_env()
struct VerificPass : public Pass {
VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -2142,7 +2166,7 @@ struct VerificPass : public Pass {
log("\n");
}
#ifdef YOSYS_ENABLE_VERIFIC
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
static bool set_verific_global_flags = true;
@@ -2175,6 +2199,9 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
+ RuntimeFlags::SetVar("veri_preserve_assignments", 1);
+ RuntimeFlags::SetVar("vhdl_preserve_assignments", 1);
+
// Workaround for VIPER #13851
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
@@ -2327,8 +2354,10 @@ struct VerificPass : public Pass {
while (argidx < GetSize(args))
file_names.Insert(args[argidx++].c_str());
- if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU))
+ if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
+ verific_error_msg.clear();
log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
+ }
verific_import_pending = true;
goto check_error;
@@ -2454,6 +2483,9 @@ struct VerificPass : public Pass {
std::set<std::string> top_mod_names;
+ InitialAssertionRewriter rw;
+ rw.RegisterCallBack();
+
if (mode_all)
{
log("Running hier_tree::ElaborateAll().\n");
@@ -2478,31 +2510,23 @@ struct VerificPass : public Pass {
if (argidx == GetSize(args))
cmd_error(args, argidx, "No top module specified.\n");
+ VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
+ VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
+
Array veri_modules, vhdl_units;
for (; argidx < GetSize(args); argidx++)
{
const char *name = args[argidx].c_str();
top_mod_names.insert(name);
- VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
-
- if (veri_lib) {
- VeriModule *veri_module = veri_lib->GetModule(name, 1);
- if (veri_module) {
- log("Adding Verilog module '%s' to elaboration queue.\n", name);
- veri_modules.InsertLast(veri_module);
- continue;
- }
- // Also elaborate all root modules since they may contain bind statements
- MapIter mi;
- FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
- if (!veri_module->IsRootModule()) continue;
- veri_modules.InsertLast(veri_module);
- }
+ VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
+ if (veri_module) {
+ log("Adding Verilog module '%s' to elaboration queue.\n", name);
+ veri_modules.InsertLast(veri_module);
+ continue;
}
- VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
- VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(name);
+ VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr;
if (vhdl_unit) {
log("Adding VHDL unit '%s' to elaboration queue.\n", name);
vhdl_units.InsertLast(vhdl_unit);
@@ -2512,6 +2536,16 @@ struct VerificPass : public Pass {
log_error("Can't find module/unit '%s'.\n", name);
}
+ if (veri_lib) {
+ // Also elaborate all root modules since they may contain bind statements
+ MapIter mi;
+ VeriModule *veri_module;
+ FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
+ if (!veri_module->IsRootModule()) continue;
+ veri_modules.InsertLast(veri_module);
+ }
+ }
+
log("Running hier_tree::Elaborate().\n");
Array *netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);
Netlist *nl;
@@ -2574,7 +2608,7 @@ struct VerificPass : public Pass {
}
#else /* YOSYS_ENABLE_VERIFIC */
- void execute(std::vector<std::string>, RTLIL::Design *) YS_OVERRIDE {
+ void execute(std::vector<std::string>, RTLIL::Design *) override {
log_cmd_error("This version of Yosys is built without Verific support.\n"
"\n"
"Use Symbiotic EDA Suite if you need Yosys+Verifc.\n"
@@ -2588,7 +2622,7 @@ struct VerificPass : public Pass {
struct ReadPass : public Pass {
ReadPass() : Pass("read", "load HDL designs") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -2629,7 +2663,7 @@ struct ReadPass : public Pass {
log("Verific support. The default is to use Verific if it is available.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
#ifdef YOSYS_ENABLE_VERIFIC
static bool verific_available = !check_noverific_env();
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-19 05:11:55 +0000