diff options
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 44 |
1 files changed, 33 insertions, 11 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 0f7f2a57a..8bd58d24c 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -651,8 +651,16 @@ wire_type_signedness: %empty; wire_type_const_rand: - TOK_CONST { current_wire_const = true; } | - TOK_RAND { current_wire_rand = true; } | + TOK_RAND TOK_CONST { + current_wire_rand = true; + current_wire_const = true; + } | + TOK_CONST { + current_wire_const = true; + } | + TOK_RAND { + current_wire_rand = true; + } | %empty; opt_wire_type_token: @@ -664,28 +672,33 @@ wire_type_token: astbuf3->children.push_back(new AstNode(AST_WIRETYPE)); astbuf3->children.back()->str = *$1; } | - TOK_WIRE { - } | TOK_WOR { astbuf3->is_wor = true; } | TOK_WAND { astbuf3->is_wand = true; } | + // wires + TOK_WIRE { + } | + TOK_WIRE logic_type { + } | + // regs TOK_REG { astbuf3->is_reg = true; } | - TOK_LOGIC { - astbuf3->is_logic = true; + TOK_VAR TOK_REG { + astbuf3->is_reg = true; } | + // logics TOK_VAR { astbuf3->is_logic = true; } | - TOK_INTEGER { - astbuf3->is_reg = true; - astbuf3->range_left = 31; - astbuf3->range_right = 0; - astbuf3->is_signed = true; + TOK_VAR logic_type { + astbuf3->is_logic = true; + } | + logic_type { + astbuf3->is_logic = true; } | TOK_GENVAR { astbuf3->type = AST_GENVAR; @@ -695,6 +708,15 @@ wire_type_token: astbuf3->range_right = 0; }; +logic_type: + TOK_LOGIC { + } | + TOK_INTEGER { + astbuf3->range_left = 31; + astbuf3->range_right = 0; + astbuf3->is_signed = true; + }; + non_opt_range: '[' expr ':' expr ']' { $$ = new AstNode(AST_RANGE); |