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-rw-r--r--frontends/verilog/const2ast.cc3
-rw-r--r--frontends/verilog/verilog_parser.y64
2 files changed, 38 insertions, 29 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index 49281f7e7..230dfadbf 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -139,6 +139,9 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
data.resize(len_in_bits, msb);
}
+ if (len_in_bits == 0)
+ log_file_error(current_filename, get_line_num(), "Illegal integer constant size of zero (IEEE 1800-2012, 5.7).\n");
+
if (len > len_in_bits)
log_warning("Literal has a width of %d bit, but value requires %d bit. (%s:%d)\n",
len_in_bits, len, current_filename.c_str(), get_line_num());
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index be2872e59..76373c2e4 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -436,9 +436,9 @@ module_arg_opt_assignment:
wire->str = ast_stack.back()->children.back()->str;
if (ast_stack.back()->children.back()->is_input) {
AstNode *n = ast_stack.back()->children.back();
- if (n->attributes.count("\\defaultvalue"))
- delete n->attributes.at("\\defaultvalue");
- n->attributes["\\defaultvalue"] = $2;
+ if (n->attributes.count(ID::defaultvalue))
+ delete n->attributes.at(ID::defaultvalue);
+ n->attributes[ID::defaultvalue] = $2;
} else
if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
@@ -521,7 +521,8 @@ package_body:
package_body_stmt:
typedef_decl |
- localparam_decl;
+ localparam_decl |
+ param_decl;
interface:
TOK_INTERFACE {
@@ -1511,24 +1512,24 @@ wire_name_and_opt_assign:
bool attr_anyseq = false;
bool attr_allconst = false;
bool attr_allseq = false;
- if (ast_stack.back()->children.back()->get_bool_attribute("\\anyconst")) {
- delete ast_stack.back()->children.back()->attributes.at("\\anyconst");
- ast_stack.back()->children.back()->attributes.erase("\\anyconst");
+ if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
+ delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
+ ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
attr_anyconst = true;
}
- if (ast_stack.back()->children.back()->get_bool_attribute("\\anyseq")) {
- delete ast_stack.back()->children.back()->attributes.at("\\anyseq");
- ast_stack.back()->children.back()->attributes.erase("\\anyseq");
+ if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
+ delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
+ ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
attr_anyseq = true;
}
- if (ast_stack.back()->children.back()->get_bool_attribute("\\allconst")) {
- delete ast_stack.back()->children.back()->attributes.at("\\allconst");
- ast_stack.back()->children.back()->attributes.erase("\\allconst");
+ if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
+ delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
+ ast_stack.back()->children.back()->attributes.erase(ID::allconst);
attr_allconst = true;
}
- if (ast_stack.back()->children.back()->get_bool_attribute("\\allseq")) {
- delete ast_stack.back()->children.back()->attributes.at("\\allseq");
- ast_stack.back()->children.back()->attributes.erase("\\allseq");
+ if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
+ delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
+ ast_stack.back()->children.back()->attributes.erase(ID::allseq);
attr_allseq = true;
}
if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
@@ -1544,7 +1545,7 @@ wire_name_and_opt_assign:
fcall->str = "\\$allconst";
if (attr_allseq)
fcall->str = "\\$allseq";
- fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
+ fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
}
} |
@@ -1552,9 +1553,9 @@ wire_name_and_opt_assign:
AstNode *wire = new AstNode(AST_IDENTIFIER);
wire->str = ast_stack.back()->children.back()->str;
if (astbuf1->is_input) {
- if (astbuf1->attributes.count("\\defaultvalue"))
- delete astbuf1->attributes.at("\\defaultvalue");
- astbuf1->attributes["\\defaultvalue"] = $3;
+ if (astbuf1->attributes.count(ID::defaultvalue))
+ delete astbuf1->attributes.at(ID::defaultvalue);
+ astbuf1->attributes[ID::defaultvalue] = $3;
}
else if (astbuf1->is_reg || astbuf1->is_logic){
AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
@@ -1735,7 +1736,6 @@ single_cell:
ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
} '(' cell_port_list ')'{
SET_AST_NODE_LOC(astbuf2, @1, @$);
- SET_AST_NODE_LOC(astbuf3, @1, @$);
};
prim_list:
@@ -1839,7 +1839,7 @@ cell_port:
attr TOK_WILDCARD_CONNECT {
if (!sv_mode)
frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
- astbuf2->attributes[ID(wildcard_port_conns)] = AstNode::mkconst_int(1, false);
+ astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
};
always_comb_or_latch:
@@ -1863,7 +1863,7 @@ always_stmt:
AstNode *node = new AstNode(AST_ALWAYS);
append_attr(node, $1);
if ($2)
- node->attributes[ID(always_ff)] = AstNode::mkconst_int(1, false);
+ node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
} always_cond {
@@ -1883,9 +1883,9 @@ always_stmt:
AstNode *node = new AstNode(AST_ALWAYS);
append_attr(node, $1);
if ($2)
- node->attributes[ID(always_latch)] = AstNode::mkconst_int(1, false);
+ node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
else
- node->attributes[ID(always_comb)] = AstNode::mkconst_int(1, false);
+ node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
AstNode *block = new AstNode(AST_BLOCK);
@@ -2355,12 +2355,12 @@ case_type:
opt_synopsys_attr:
opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
- if (ast_stack.back()->attributes.count("\\full_case") == 0)
- ast_stack.back()->attributes["\\full_case"] = AstNode::mkconst_int(1, false);
+ if (ast_stack.back()->attributes.count(ID::full_case) == 0)
+ ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
} |
opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
- if (ast_stack.back()->attributes.count("\\parallel_case") == 0)
- ast_stack.back()->attributes["\\parallel_case"] = AstNode::mkconst_int(1, false);
+ if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
+ ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
} |
/* empty */;
@@ -2522,6 +2522,7 @@ gen_stmt:
} simple_behavioral_stmt ';' expr {
ast_stack.back()->children.push_back($6);
} ';' simple_behavioral_stmt ')' gen_stmt_block {
+ SET_AST_NODE_LOC(ast_stack.back(), @1, @11);
ast_stack.pop_back();
} |
TOK_IF '(' expr ')' {
@@ -2530,6 +2531,7 @@ gen_stmt:
ast_stack.push_back(node);
ast_stack.back()->children.push_back($3);
} gen_stmt_block opt_gen_else {
+ SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
ast_stack.pop_back();
} |
case_type '(' expr ')' {
@@ -2538,6 +2540,7 @@ gen_stmt:
ast_stack.push_back(node);
} gen_case_body TOK_ENDCASE {
case_type_stack.pop_back();
+ SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
ast_stack.pop_back();
} |
TOK_BEGIN {
@@ -2551,6 +2554,7 @@ gen_stmt:
exitTypeScope();
delete $3;
delete $7;
+ SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
ast_stack.pop_back();
} |
TOK_MSG_TASKS {
@@ -2560,6 +2564,7 @@ gen_stmt:
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
} opt_arg_list ';'{
+ SET_AST_NODE_LOC(ast_stack.back(), @1, @3);
ast_stack.pop_back();
};
@@ -2569,6 +2574,7 @@ gen_stmt_block:
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
} gen_stmt_or_module_body_stmt {
+ SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
ast_stack.pop_back();
};
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-24 08:33:05 +0000