diff options
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/lexer.l | 4 | ||||
| -rw-r--r-- | frontends/verilog/parser.y | 2 | ||||
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 10 |
3 files changed, 13 insertions, 3 deletions
diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l index a269c072a..f899191bb 100644 --- a/frontends/verilog/lexer.l +++ b/frontends/verilog/lexer.l @@ -184,7 +184,7 @@ supply1 { return TOK_SUPPLY1; } "$signed" { return TOK_TO_SIGNED; } "$unsigned" { return TOK_TO_UNSIGNED; } -[a-zA-Z_$][a-zA-Z0-9_$]* { +[a-zA-Z_$][a-zA-Z0-9_\.$]* { frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); return TOK_ID; } @@ -233,6 +233,8 @@ supply1 { return TOK_SUPPLY1; } "<=" { return OP_LE; } ">=" { return OP_GE; } +"===" { return OP_EQ; } + /* "~&" { return OP_NAND; } */ /* "~|" { return OP_NOR; } */ "~^" { return OP_XNOR; } diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index 9caa236f8..22af178e8 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -607,7 +607,7 @@ always_stmt: ast_stack.pop_back(); } | attr TOK_INITIAL { - AstNode *node = new AstNode(AST_ALWAYS); + AstNode *node = new AstNode(AST_INITIAL); append_attr(node, $1); ast_stack.back()->children.push_back(node); ast_stack.push_back(node); diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index f4a8c79fa..f9731cbc2 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -89,6 +89,9 @@ struct VerilogFrontend : public Frontend { log(" -nopp\n"); log(" do not run the pre-processor\n"); log("\n"); + log(" -lib\n"); + log(" only create empty placeholder modules\n"); + log("\n"); } virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) { @@ -100,6 +103,7 @@ struct VerilogFrontend : public Frontend { bool flag_mem2reg = false; bool flag_ppdump = false; bool flag_nopp = false; + bool flag_lib = false; frontend_verilog_yydebug = false; log_header("Executing Verilog-2005 frontend.\n"); @@ -144,6 +148,10 @@ struct VerilogFrontend : public Frontend { flag_nopp = true; continue; } + if (arg == "-lib") { + flag_lib = true; + continue; + } break; } extra_args(f, filename, args, argidx); @@ -173,7 +181,7 @@ struct VerilogFrontend : public Frontend { frontend_verilog_yyparse(); frontend_verilog_yylex_destroy(); - AST::process(design, current_ast, flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg); + AST::process(design, current_ast, flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib); if (!flag_nopp) fclose(fp); |