break;

case AST_CASE:

fprintf(f, "%s" "casex (", indent.c_str());

fprintf(f, "%s" "casez (", indent.c_str());

else

fprintf(f, "%s" "case (", indent.c_str());

}

} else {

log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());

}

// simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.

// it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()

bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param);

AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init);

void expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map, bool original_scope = true);

void replace_ids(const std::string &prefix, const std::map<std::string, std::string> &rules);

// additional functionality for evaluating constant functions

struct varinfo_t { RTLIL::Const val; int offset; bool is_signed; };

bool has_const_only_constructs(bool &recommend_const_eval);

void replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall);

AstNode *eval_const_function(AstNode *fcall);

bool is_simple_const_expr();

AST::AstNode *AST::dpi_call(const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<AstNode*> &args)

{

AST::AstNode *newNode = nullptr;

ffi_type *types [args.size() + 1];

void *values [args.size() + 1];

ffi_cif cif;

value_store[i].i32 = args[i]->asInt(args[i]->is_signed);

values[i] = &value_store[i].i32;

types[i] = &ffi_type_sint32;

} else {

log_error("invalid argtype '%s' for argument %d.\n", argtypes[i].c_str(), i);

}

} else if (rtype == "real") {

types[args.size()] = &ffi_type_double;

values[args.size()] = &value_store[args.size()].f64;

} else {

log_error("invalid rtype '%s'.\n", rtype.c_str());

}

newNode = new AstNode(AST_REALVALUE);

newNode->realvalue = value_store[args.size()].f32;

log(" return realvalue: %g\n", newNode->asReal(true));

} else {

newNode = AstNode::mkconst_int(value_store[args.size()].i32, false);

log(" return integer: %lld\n", (long long)newNode->asInt(true));

RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);

wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column);

for (auto &attr : that->attributes) {

if (attr.second->type != AST_CONSTANT)

RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());

wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column);

for (auto &attr : that->attributes) {

if (attr.second->type != AST_CONSTANT)

}

if (child->type == AST_ARGUMENT) {

RTLIL::SigSpec sig;

if (child->str.size() == 0) {

char buf[100];

snprintf(buf, 100, "$%d", ++port_counter);

current_block = this;

current_block_child = children[i];

}

if ((type == AST_ALWAYS || type == AST_INITIAL) && children[i]->type == AST_BLOCK)

current_top_block = children[i];

if (i == 0 && child_0_is_self_determined)

if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) {

// replace with wire representing the packed structure

newNode = make_packed_struct(template_node, str);

current_scope[str] = this;

goto apply_newNode;

}

if (all_args_const) {

AstNode *func_workspace = current_scope[str]->clone();

newNode = func_workspace->eval_const_function(this);

delete func_workspace;

goto apply_newNode;

wire->type = AST_LOCALPARAM;

wire->attributes.erase(ID::nosync);

wire->children.insert(wire->children.begin(), arg->clone());

continue;

}

AstNode *wire_id = new AstNode(AST_IDENTIFIER);

if (current_scope[str]->children[0]->isConst())

newNode = current_scope[str]->children[0]->clone();

}

newNode = mkconst_int(0, sign_hint, width_hint);

}

break;

return did_something;

}

{

}

// replace a readmem[bh] TCALL ast node with a block of memory assignments

name_map[child->str] = new_name;

if (child->type == AST_FUNCTION)

else

child->str = new_name;

current_scope[new_name] = child;

bool AstNode::has_const_only_constructs(bool &recommend_const_eval)

{

if (type == AST_FOR)

recommend_const_eval = true;

if (type == AST_WHILE || type == AST_REPEAT)

return true;

if (type == AST_FCALL && current_scope.count(str))

return true;

for (auto child : children)

return true;

return false;

}

"\\"[^ \t\r\n]+ { rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; }

"$"[^ \t\r\n]+ { rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; }

[0-9]+'[01xzm-]* { rtlil_frontend_yylval.string = strdup(yytext); return TOK_VALUE; }

-?[0-9]+ {

#include "VeriLibrary.h"

#include "VeriExtensions.h"

#endif

#endif

#ifdef __clang__

continue;

}

{

SigBit initstate = module->Initstate(new_verific_id(inst));

SigBit sig_o = net_map_at(inst->GetOutput());

log("\n");

log(" verific -app <application>..\n");

log("\n");

log("\n");

log("Application options:\n");

log("\n");

log(" WARNING: Templates only available in commercial build.\n");

log("\n");

#endif

log("\n");

log("\n");

}

#ifdef YOSYS_ENABLE_VERIFIC

if (check_noverific_env())

log_cmd_error("This version of Yosys is built without Verific support.\n"

"\n"

"\n"

log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n");

void execute(std::vector<std::string>, RTLIL::Design *) override {

log_cmd_error("This version of Yosys is built without Verific support.\n"

"\n"

"\n"

}

#endif

} VerificPass;

define_map_t::define_map_t()

{

add("YOSYS", "1");

}

// We must define this destructor here (rather than relying on the default), because we need to

// the argument list); false if we finished with ','.

static bool read_argument(std::string &dest)

{

std::vector<char> openers;

for (;;) {

std::string tok = next_token(true);

if (tok == ")") {

return true;

if (openers.back() != '(')

log_error("Mismatched brackets in macro argument: %c and %c.\n",

openers.back(), tok[0]);

}

break;

}

extra_args(f, filename, args, argidx);

log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str());

%token TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AND_ASSIGN TOK_SUB_ASSIGN

%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int

%type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number

%type <string> type_name

%type <ast> opt_enum_init enum_type struct_type non_wire_data_type

delay:

non_opt_delay | %empty;

wire_type_token_io:

TOK_INPUT {

astbuf3->is_output = true;

};

wire_type_token:

} |

TOK_WOR {

astbuf3->is_wor = true;

TOK_WAND {

astbuf3->is_wand = true;

} |

TOK_REG {

astbuf3->is_reg = true;

} |

} |

TOK_VAR {

astbuf3->is_logic = true;

} |

} |

TOK_GENVAR {

astbuf3->type = AST_GENVAR;

astbuf3->is_signed = true;

astbuf3->range_left = 31;

astbuf3->range_right = 0;

} |

astbuf3->is_signed = true;

};

non_opt_range:

task_func_port:

attr wire_type range {

if (albuf) {

delete astbuf1;

if (astbuf2 != NULL)

delete astbuf2;

albuf = $1;

astbuf1 = $2;

astbuf2 = checkRange(astbuf1, $3);

} wire_name |

{

if (!astbuf1) {

;

typedef_decl:

astbuf1 = $2;

astbuf2 = checkRange(astbuf1, $3);

if (astbuf2)