aboutsummaryrefslogtreecommitdiffstats
path: root/frontends
diff options
context:
space:
mode:
Diffstat (limited to 'frontends')
-rw-r--r--frontends/aiger/aigerparse.cc2
-rw-r--r--frontends/ast/ast.cc2
-rw-r--r--frontends/ast/genrtlil.cc20
-rw-r--r--frontends/ast/simplify.cc43
-rw-r--r--frontends/ilang/ilang_lexer.l13
-rw-r--r--frontends/ilang/ilang_parser.y11
-rw-r--r--frontends/verilog/verilog_parser.y4
7 files changed, 71 insertions, 24 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index cbce0c990..92cf92fa8 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -30,7 +30,9 @@
#include <libkern/OSByteOrder.h>
#define __builtin_bswap32 OSSwapInt32
#endif
+#ifndef __STDC_FORMAT_MACROS
#define __STDC_FORMAT_MACROS
+#endif
#include <inttypes.h>
#include "kernel/yosys.h"
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 2b6002548..245a53611 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1153,6 +1153,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire)
{
current_ast = ast;
+ current_ast_mod = nullptr;
flag_dump_ast1 = dump_ast1;
flag_dump_ast2 = dump_ast2;
flag_no_dump_ptr = no_dump_ptr;
@@ -1219,6 +1220,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
}
design->add(process_module(*it, defer));
+ current_ast_mod = nullptr;
}
else if ((*it)->type == AST_PACKAGE) {
// process enum/other declarations
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index c0539252c..ab368fdb0 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1326,20 +1326,25 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
{
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
+ is_signed = sign_hint;
RTLIL::SigSpec cond = children[0]->genRTLIL();
RTLIL::SigSpec sig;
- if (cond.is_fully_const()) {
+
+ if (cond.is_fully_def())
+ {
if (cond.as_bool()) {
sig = children[1]->genRTLIL(width_hint, sign_hint);
- widthExtend(this, sig, sig.size(), children[1]->is_signed);
- }
- else {
+ log_assert(is_signed == children[1]->is_signed);
+ } else {
sig = children[2]->genRTLIL(width_hint, sign_hint);
- widthExtend(this, sig, sig.size(), children[2]->is_signed);
+ log_assert(is_signed == children[2]->is_signed);
}
+
+ widthExtend(this, sig, sig.size(), is_signed);
}
- else {
+ else
+ {
RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
@@ -1347,7 +1352,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false);
int width = max(val1.size(), val2.size());
- is_signed = children[1]->is_signed && children[2]->is_signed;
+ log_assert(is_signed == children[1]->is_signed);
+ log_assert(is_signed == children[2]->is_signed);
widthExtend(this, val1, width, is_signed);
widthExtend(this, val2, width, is_signed);
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index b87af0f8c..372dcf95c 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -420,9 +420,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
current_scope[node->str] = node;
for (auto enode : node->children) {
log_assert(enode->type==AST_ENUM_ITEM);
- if (current_scope.count(enode->str) == 0) {
+ if (current_scope.count(enode->str) == 0)
current_scope[enode->str] = enode;
- }
+ else
+ log_file_error(filename, location.first_line, "enum item %s already exists\n", enode->str.c_str());
}
}
}
@@ -441,6 +442,29 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
}
}
+ // create name resolution entries for all objects with names
+ if (type == AST_PACKAGE) {
+ //add names to package scope
+ for (size_t i = 0; i < children.size(); i++) {
+ AstNode *node = children[i];
+ // these nodes appear at the top level in a package and can define names
+ if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_TYPEDEF) {
+ current_scope[node->str] = node;
+ }
+ if (node->type == AST_ENUM) {
+ current_scope[node->str] = node;
+ for (auto enode : node->children) {
+ log_assert(enode->type==AST_ENUM_ITEM);
+ if (current_scope.count(enode->str) == 0)
+ current_scope[enode->str] = enode;
+ else
+ log_file_error(filename, location.first_line, "enum item %s already exists in package\n", enode->str.c_str());
+ }
+ }
+ }
+ }
+
+
auto backup_current_block = current_block;
auto backup_current_block_child = current_block_child;
auto backup_current_top_block = current_top_block;
@@ -907,9 +931,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
);
}
//start building attribute string
- std::string enum_item_str = "\\enum_";
- enum_item_str.append(std::to_string(width));
- enum_item_str.append("_");
+ std::string enum_item_str = "\\enum_value_";
//get enum item value
if(enum_item->children[0]->type != AST_CONSTANT){
log_error("expected const, got %s for %s (%s)\n",
@@ -917,8 +939,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
enum_item->str.c_str(), enum_node->str.c_str()
);
}
- int val = enum_item->children[0]->asInt(is_signed);
- enum_item_str.append(std::to_string(val));
+ RTLIL::Const val = enum_item->children[0]->bitsAsConst(width, is_signed);
+ enum_item_str.append(val.as_string());
//set attribute for available val to enum item name mappings
attributes[enum_item_str.c_str()] = mkconst_str(enum_item->str);
}
@@ -1147,7 +1169,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
// annotate identifiers using scope resolution and create auto-wires as needed
if (type == AST_IDENTIFIER) {
if (current_scope.count(str) == 0) {
- for (auto node : current_ast_mod->children) {
+ AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod;
+ for (auto node : current_scope_ast->children) {
//log("looking at mod scope child %s\n", type2str(node->type).c_str());
switch (node->type) {
case AST_PARAMETER:
@@ -1181,7 +1204,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
}
}
if (current_scope.count(str) == 0) {
- if (flag_autowire || str == "\\$global_clock") {
+ if (current_ast_mod == nullptr) {
+ log_file_error(filename, location.first_line, "Identifier `%s' is implicitly declared outside of a module.\n", str.c_str());
+ } else if (flag_autowire || str == "\\$global_clock") {
AstNode *auto_wire = new AstNode(AST_AUTOWIRE);
auto_wire->str = str;
current_ast_mod->children.push_back(auto_wire);
diff --git a/frontends/ilang/ilang_lexer.l b/frontends/ilang/ilang_lexer.l
index 4fd0ae855..62f53d18e 100644
--- a/frontends/ilang/ilang_lexer.l
+++ b/frontends/ilang/ilang_lexer.l
@@ -29,6 +29,7 @@
#pragma clang diagnostic ignored "-Wdeprecated-register"
#endif
+#include <cstdlib>
#include "frontends/ilang/ilang_frontend.h"
#include "ilang_parser.tab.hh"
@@ -88,7 +89,16 @@ USING_YOSYS_NAMESPACE
"."[0-9]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; }
[0-9]+'[01xzm-]* { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_VALUE; }
--?[0-9]+ { rtlil_frontend_ilang_yylval.integer = atoi(yytext); return TOK_INT; }
+-?[0-9]+ {
+ char *end = nullptr;
+ long value = strtol(yytext, &end, 10);
+ if (end != yytext + strlen(yytext))
+ return TOK_INVALID; // literal out of range of long
+ if (value < INT_MIN || value > INT_MAX)
+ return TOK_INVALID; // literal out of range of int (relevant mostly for LP64 platforms)
+ rtlil_frontend_ilang_yylval.integer = value;
+ return TOK_INT;
+}
\" { BEGIN(STRING); }
<STRING>\\. { yymore(); }
@@ -136,4 +146,3 @@ USING_YOSYS_NAMESPACE
void *rtlil_frontend_ilang_avoid_input_warnings() {
return (void*)&yyinput;
}
-
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index 4e0b62edd..0522fa72a 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -169,7 +169,7 @@ wire_stmt:
current_wire->attributes = attrbuf;
attrbuf.clear();
} wire_options TOK_ID EOL {
- if (current_module->wires_.count($4) != 0)
+ if (current_module->wire($4) != nullptr)
rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of wire %s.", $4).c_str());
current_module->rename(current_wire, $4);
free($4);
@@ -179,6 +179,9 @@ wire_options:
wire_options TOK_WIDTH TOK_INT {
current_wire->width = $3;
} |
+ wire_options TOK_WIDTH TOK_INVALID {
+ rtlil_frontend_ilang_yyerror("ilang error: invalid wire width");
+ } |
wire_options TOK_UPTO {
current_wire->upto = true;
} |
@@ -229,7 +232,7 @@ memory_options:
cell_stmt:
TOK_CELL TOK_ID TOK_ID EOL {
- if (current_module->cells_.count($3) != 0)
+ if (current_module->cell($3) != nullptr)
rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell %s.", $3).c_str());
current_cell = current_module->addCell($3, $2);
current_cell->attributes = attrbuf;
@@ -424,9 +427,9 @@ sigspec:
delete $1;
} |
TOK_ID {
- if (current_module->wires_.count($1) == 0)
+ if (current_module->wire($1) == nullptr)
rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
- $$ = new RTLIL::SigSpec(current_module->wires_[$1]);
+ $$ = new RTLIL::SigSpec(current_module->wire($1));
free($1);
} |
sigspec '[' TOK_INT ']' {
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 3bffa3986..76373c2e4 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -521,7 +521,8 @@ package_body:
package_body_stmt:
typedef_decl |
- localparam_decl;
+ localparam_decl |
+ param_decl;
interface:
TOK_INTERFACE {
@@ -1735,7 +1736,6 @@ single_cell:
ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
} '(' cell_port_list ')'{
SET_AST_NODE_LOC(astbuf2, @1, @$);
- SET_AST_NODE_LOC(astbuf3, @1, @$);
};
prim_list:
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-17 14:46:04 +0000