diff options
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/ast.cc | 2 | ||||
| -rw-r--r-- | frontends/ast/genrtlil.cc | 6 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 22 | ||||
| -rw-r--r-- | frontends/verific/README | 8 |
4 files changed, 33 insertions, 5 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 7fb61bb34..af5e326ad 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -317,6 +317,8 @@ void AstNode::dumpAst(FILE *f, std::string indent) const fprintf(f, " reg"); if (is_signed) fprintf(f, " signed"); + if (is_unsized) + fprintf(f, " unsized"); if (basic_prep) fprintf(f, " basic_prep"); if (lookahead) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d4299bf69..e0a522430 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1000,6 +1000,12 @@ void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real if (found_real) *found_real = false; detectSignWidthWorker(width_hint, sign_hint, found_real); + + constexpr int kWidthLimit = 1 << 24; + if (width_hint >= kWidthLimit) + log_file_error(filename, location.first_line, + "Expression width %d exceeds implementation limit of %d!\n", + width_hint, kWidthLimit); } static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id, diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 5c4dd290f..e7f897b3c 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -915,6 +915,22 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } } + if (type == AST_ARGUMENT) + { + if (children.size() == 1 && children[0]->type == AST_CONSTANT) + { + // HACK: For port bindings using unbased unsized literals, mark them + // signed so they sign-extend. The hierarchy will still incorrectly + // generate a warning complaining about resizing the expression. + // This also doesn't handle the complex of something like a ternary + // expression bound to a port, where the actual size of the port is + // needed to resolve the expression correctly. + AstNode *arg = children[0]; + if (arg->is_unsized) + arg->is_signed = true; + } + } + int backup_width_hint = width_hint; bool backup_sign_hint = sign_hint; @@ -3773,7 +3789,11 @@ replace_fcall_later:; case AST_CAST_SIZE: if (children.at(0)->type == AST_CONSTANT && children.at(1)->type == AST_CONSTANT) { int width = children[0]->bitsAsConst().as_int(); - RTLIL::Const val = children[1]->bitsAsConst(width); + RTLIL::Const val; + if (children[1]->is_unsized) + val = children[1]->bitsAsUnsizedConst(width); + else + val = children[1]->bitsAsConst(width); newNode = mkconst_bits(val.bits, children[1]->is_signed); } break; diff --git a/frontends/verific/README b/frontends/verific/README index c37d76343..952fb1e0c 100644 --- a/frontends/verific/README +++ b/frontends/verific/README @@ -1,11 +1,11 @@ This directory contains Verific bindings for Yosys. -Use Symbiotic EDA Suite if you need Yosys+Verifc. -https://www.symbioticeda.com/seda-suite +Use Tabby CAD Suite from YosysHQ if you need Yosys+Verifc. +https://www.yosyshq.com/ -Contact office@symbioticeda.com for free evaluation -binaries of Symbiotic EDA Suite. +Contact YosysHQ at contact@yosyshq.com for free evaluation +binaries of Tabby CAD Suite. Verific Features that should be enabled in your Verific library |