/*

* yosys -- Yosys Open SYnthesis Suite

*

* 2019 Eddie Hung <eddie@fpgeh.com>

*

* Permission to use, copy, modify, and/or distribute this software for any

#define log_debug2(...) ;

//#define log_debug2(...) log_debug(__VA_ARGS__)

struct ConstEvalAig

{

RTLIL::Module *module;

unsigned l1, l2, l3;

// Parse inputs

for (unsigned i = 1; i <= I; ++i, ++line_count) {

if (!(f >> l1))

log_error("Line %u cannot be interpreted as an input!\n", line_count);

clk_wire->port_input = true;

clk_wire->port_output = false;

}

for (unsigned i = 0; i < L; ++i, ++line_count) {

if (!(f >> l1 >> l2))

log_error("Line %u cannot be interpreted as a latch!\n", line_count);

}

// Parse outputs

for (unsigned i = 0; i < O; ++i, ++line_count) {

if (!(f >> l1))

log_error("Line %u cannot be interpreted as an output!\n", line_count);

std::string line;

// Parse inputs

for (unsigned i = 1; i <= I; ++i) {

log_debug2("%d is an input\n", i);

RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, i));

clk_wire->port_input = true;

clk_wire->port_output = false;

}

l1 = (I+1) * 2;

for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) {

if (!(f >> l2))

}

// Parse outputs

for (unsigned i = 0; i < O; ++i, ++line_count) {

if (!(f >> l1))

log_error("Line %u cannot be interpreted as an output!\n", line_count);

/*

* yosys -- Yosys Open SYnthesis Suite

*

* 2019 Eddie Hung <eddie@fpgeh.com>

*

* Permission to use, copy, modify, and/or distribute this software for any

OBJS += frontends/ast/simplify.o

OBJS += frontends/ast/genrtlil.o

OBJS += frontends/ast/dpicall.o

/*

* yosys -- Yosys Open SYnthesis Suite

*

* Copyright (C) 2018 Ruben Undheim <ruben.undheim@gmail.com>

*

* Permission to use, copy, modify, and/or distribute this software for any

const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;

RTLIL::SigSpec ignoreThisSignalsInInitial;

AstNode *current_always, *current_top_block, *current_block, *current_block_child;

bool current_always_clocked;

}

// convert node types to string

X(AST_STRUCT)

X(AST_UNION)

X(AST_STRUCT_ITEM)

#undef X

default:

log_abort();

// create new node (AstNode constructor)

// (the optional child arguments make it easier to create AST trees)

{

static unsigned int hashidx_count = 123456789;

hashidx_count = mkhash_xorshift(hashidx_count);

children.push_back(child2);

if (child3)

children.push_back(child3);

}

// create a (deep recursive) copy of a node

}

std::string type_name = type2str(type);

if (!flag_no_dump_ptr) {

if (id2ast)

fprintf(f, " reg");

if (is_signed)

fprintf(f, " signed");

if (basic_prep)

fprintf(f, " basic_prep");

if (lookahead)

fprintf(f, " %d", v);

fprintf(f, " ]");

}

if (is_enum) {

fprintf(f, " type=enum");

}

break;

case AST_CASE:

fprintf(f, "%s" "casex (", indent.c_str());

fprintf(f, "%s" "casez (", indent.c_str());

else

fprintf(f, "%s" "case (", indent.c_str());

return bitsAsConst(width, is_signed);

}

{

log_assert(type == AST_CONSTANT);

return val;

}

{

RTLIL::Const val = asAttrConst();

if (is_signed)

val.flags |= RTLIL::CONST_FLAG_SIGNED;

return result;

}

{

log_assert(current_scope.empty());

log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE);

log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());

}

current_ast_mod = ast;

AstNode *ast_before_simplify;

if (!defer)

{

bool blackbox_module = flag_lib;

if (!blackbox_module && !flag_noblackbox) {

}

}

while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { }

if (flag_dump_ast2) {

log("Dumping AST after simplification:\n");

for (auto &attr : ast->attributes) {

if (attr.second->type != AST_CONSTANT)

log_file_error(ast->filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());

}

for (size_t i = 0; i < ast->children.size(); i++) {

AstNode *node = ast->children[i];

for (auto &attr : ast->attributes) {

if (attr.second->type != AST_CONSTANT)

continue;

}

}

if (ast->type == AST_INTERFACE)

if (flag_dump_rtlil) {

log("Dumping generated RTLIL:\n");

log("--- END OF RTLIL DUMP ---\n");

}

return current_module;

}

// create AstModule instances for all modules in the AST tree and add them to 'design'

void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,

bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire)

flag_autowire = autowire;

log_assert(current_ast->type == AST_DESIGN);

{

{

for (auto n : design->verilog_globals)

// append nodes from previous packages using package-qualified names

for (auto &n : design->verilog_packages) {

} else {

cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1);

}

}

}

if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {

} else if (nooverwrite) {

continue;

} else {

existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "",

design->remove(existing_mod);

}

}

current_ast_mod = nullptr;

}

// process enum/other declarations

current_scope.clear();

}

else {

// must be global definition

current_scope.clear();

}

}

}

}

// When an interface instance is found in a module, the whole RTLIL for the module will be rederived again

// from AST. The interface members are copied into the AST module with the prefix of the interface.

{

loadconfig();

AstNode *new_ast = ast->clone();

for (auto &intf : local_interfaces) {

std::string intfname = intf.first.str();

}

}

// Set the attribute "interfaces_replaced_in_module" so that it does not happen again.

}

// create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces

explode_interface_port(new_ast, intfmodule, intfname, modport);

}

design->module(modname)->check();

RTLIL::Module* mod = design->module(modname);

}

} else {

log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());

}

if (!design->has(modname)) {

new_ast->str = modname;

design->module(modname)->check();

} else if (!quiet) {

log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());

return modname;

}

// create a new parametric module (when needed) and return the name of the generated module

std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet)

{

if (stripped_name.compare(0, 9, "$abstract") == 0)

stripped_name = stripped_name.substr(9);

int para_counter = 0;

for (const auto child : ast->children) {

if (child->type != AST_PARAMETER)

continue;

if (it != parameters.end()) {

if (!quiet)

log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second));

continue;

}

it = parameters.find(stringf("$%d", para_counter));

if (it != parameters.end()) {

if (!quiet)

log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second));

continue;

}

}

if (design->has(modname))

return modname;

}

continue;

rewrite_parameter:

delete child->children.at(0);

if ((it->second.flags & RTLIL::CONST_FLAG_REAL) != 0) {

child->children[0] = new AstNode(AST_REALVALUE);

/* -*- c++ -*-

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

AST_TYPEDEF,

AST_STRUCT,

AST_UNION,

};

struct AstSrcLocType {

// if this is a multirange memory then this vector contains offset and length of each dimension

std::vector<int> multirange_dimensions;

// this is set by simplify and used during RTLIL generation

AstNode *id2ast;

AstSrcLocType location;

// creating and deleting nodes

AstNode *clone() const;

void cloneInto(AstNode *other) const;

void delete_children();

// simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.

// it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()

bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param);

AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init);

void mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places,

dict<AstNode*, uint32_t> &mem2reg_flags, dict<AstNode*, uint32_t> &proc_flags, uint32_t &status_flags);

bool mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block, AstNode *&async_block);

void mem2reg_remove(pool<AstNode*> &mem2reg_set, vector<AstNode*> &delnodes);

void meminfo(int &mem_width, int &mem_size, int &addr_bits);

bool detect_latch(const std::string &var);

// additional functionality for evaluating constant functions

bool is_simple_const_expr();

std::string process_format_str(const std::string &sformat, int next_arg, int stage, int width_hint, bool sign_hint);

// create a human-readable text representation of the AST (for debugging)

void dumpAst(FILE *f, std::string indent) const;

void dumpVlog(FILE *f, std::string indent) const;

// used by genRTLIL() for detecting expression width and sign

void detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real = NULL);

void detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real = NULL);

// for expressions the resulting signal vector is returned

// all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module

RTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false);

// compare AST nodes

bool operator==(const AstNode &other) const;

RTLIL::Const bitsAsConst(int width, bool is_signed);

RTLIL::Const bitsAsConst(int width = -1);

RTLIL::Const bitsAsUnsizedConst(int width);

uint64_t asInt(bool is_signed);

bool bits_only_01() const;

bool asBool() const;

// helpers for enum

void allocateDefaultEnumValues();

void annotateTypedEnums(AstNode *template_node);

};

// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code

RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) override;

RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;

std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet = false);

RTLIL::Module *clone() const override;

void loadconfig() const;

};

std::pair<std::string,std::string> split_modport_from_type(std::string name_type);

AstNode * find_modport(AstNode *intf, std::string name);

void explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport);

}

namespace AST_INTERNAL

extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;

extern RTLIL::SigSpec ignoreThisSignalsInInitial;

extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child;

extern bool current_always_clocked;

struct LookaheadRewriter;

struct ProcessGenerator;

}

YOSYS_NAMESPACE_END

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

AST::AstNode *AST::dpi_call(const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<AstNode*> &args)

{

AST::AstNode *newNode = nullptr;

ffi_type *types [args.size() + 1];

void *values [args.size() + 1];

ffi_cif cif;

value_store[i].i32 = args[i]->asInt(args[i]->is_signed);

values[i] = &value_store[i].i32;

types[i] = &ffi_type_sint32;

} else {

log_error("invalid argtype '%s' for argument %d.\n", argtypes[i].c_str(), i);

}

} else if (rtype == "real") {

types[args.size()] = &ffi_type_double;

values[args.size()] = &value_store[args.size()].f64;

} else {

log_error("invalid rtype '%s'.\n", rtype.c_str());

}

newNode = new AstNode(AST_REALVALUE);

newNode->realvalue = value_store[args.size()].f32;

log(" return realvalue: %g\n", newNode->asReal(true));

} else {

newNode = AstNode::mkconst_int(value_store[args.size()].i32, false);

log(" return integer: %lld\n", (long long)newNode->asInt(true));

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

#include "kernel/log.h"

#include "kernel/utils.h"

#include "libs/sha1/sha1.h"

#include "ast.h"

#include <sstream>

#include <stdarg.h>

{

IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);

RTLIL::Cell *cell = current_module->addCell(name, type);

RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);

if (gen_attributes)

for (auto &attr : that->attributes) {

IdString name = stringf("$extend$%s:%d$%d", that->filename.c_str(), that->location.first_line, autoidx++);

RTLIL::Cell *cell = current_module->addCell(name, ID($pos));

RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);

if (that != NULL)

for (auto &attr : that->attributes) {

{

IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);

RTLIL::Cell *cell = current_module->addCell(name, type);

RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);

for (auto &attr : that->attributes) {

if (attr.second->type != AST_CONSTANT)

sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);

RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux));

RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());

for (auto &attr : that->attributes) {

if (attr.second->type != AST_CONSTANT)

LookaheadRewriter la_rewriter(always);

// generate process and simple root case

for (auto &attr : always->attributes) {

if (attr.second->type != AST_CONSTANT)

log_file_error(always->filename, always->location.first_line, "Attribute `%s' with non-constant value!\n",

attr.first.c_str());

proc->attributes[attr.first] = attr.second->asAttrConst();

}

current_case = &proc->root_case;

// create initial temporary signal for all output registers

if (found_anyedge_syncs) {

if (found_global_syncs)

log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n");

log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");

log("use of @* instead of @(...) for better match of synthesis and simulation.\n");

}

if (child->type == AST_BLOCK)

processAst(child);

if (initSyncSignals.size() > 0)

{

RTLIL::SyncRule *sync = new RTLIL::SyncRule;

} while (current_module->wires_.count(wire_name) > 0);

RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);

chunk.wire = wire;

chunk.offset = 0;

case AST_ASSIGN_LE:

{

RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue;

pool<SigBit> lvalue_sigbits;

for (int i = 0; i < GetSize(lvalue); i++) {

case AST_CASE:

{

RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;

current_case->switches.push_back(sw);

for (auto &attr : ast->attributes) {

RTLIL::CaseRule *backup_case = current_case;

current_case = new RTLIL::CaseRule;

last_generated_case = current_case;

addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);

for (auto node : child->children) {

else if (node->type == AST_BLOCK)

processAst(node);

else

}

if (default_case != current_case)

sw->cases.push_back(current_case);

log_abort();

}

}

};

// detect sign and width of an expression

void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real)

{

case AST_IDENTIFIER:

id_ast = id2ast;

if (!id_ast)

log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", str.c_str());

if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) {

this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;

if (children.size() > 1)

range = children[1];

} else

log_file_error(filename, location.first_line, "Failed to detect width for identifier %s!\n", str.c_str());

if (range) {

if (children.at(0)->type != AST_CONSTANT)

log_file_error(filename, location.first_line, "Static cast with non constant expression!\n");

children.at(1)->detectSignWidthWorker(width_hint, sign_hint);

if (width_hint <= 0)

log_file_error(filename, location.first_line, "Static cast with zero or negative size!\n");

break;

width_hint = max(width_hint, this_width);

break;

case AST_FCALL:

if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {

if (GetSize(children) == 1) {

}

break;

}

YS_FALLTHROUGH

// everything should have been handled above -> print error if not.

default:

for (auto f : log_files)

log_file_error(filename, location.first_line, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());

}

if (found_real)

*found_real = false;

detectSignWidthWorker(width_hint, sign_hint, found_real);

}

// create RTLIL from an AST node

// If a port in a module with unknown type is found, mark it with the attribute 'is_interface'

// This is used by the hierarchy pass to know when it can replace interface connection with the individual

// signals.

wire->start_offset = 0;

wire->port_id = port_id;

wire->port_input = true;

log_file_error(filename, location.first_line, "Parameter `%s' with non-constant value!\n", str.c_str());

RTLIL::Const val = children[0]->bitsAsConst();

current_module->connect(wire, val);

wire->attributes[type == AST_PARAMETER ? ID::parameter : ID::localparam] = 1;

for (auto &attr : attributes) {

// create an RTLIL::Wire for an AST_WIRE node

case AST_WIRE: {

if (!range_valid)

log_file_error(filename, location.first_line, "Signal `%s' with non-constant width!\n", str.c_str());

if (!(range_left + 1 >= range_right))

log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);

wire->start_offset = range_right;

wire->port_id = port_id;

wire->port_input = is_input;

// create an RTLIL::Memory for an AST_MEMORY node

case AST_MEMORY: {

log_assert(children.size() >= 2);

log_assert(children[0]->type == AST_RANGE);

log_assert(children[1]->type == AST_RANGE);

log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str());

RTLIL::Memory *memory = new RTLIL::Memory;

memory->name = str;

memory->width = children[0]->range_left - children[0]->range_right + 1;

if (children[1]->range_right < children[1]->range_left) {

memory->start_offset = children[1]->range_left;

memory->size = children[1]->range_right - children[1]->range_left + 1;

}

current_module->memories[memory->name] = memory;

for (auto &attr : attributes) {

if (id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {

RTLIL::Wire *wire = current_module->addWire(str);

wire->name = str;

log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str());

else

log_file_error(filename, location.first_line, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());

// changing the size of signal can be done directly using RTLIL::SigSpec

case AST_CAST_SIZE: {

RTLIL::SigSpec size = children[0]->genRTLIL();

if (!size.is_fully_const())

log_file_error(filename, location.first_line, "Static cast with non constant expression!\n");

int width = size.as_int();

if (width <= 0)

log_file_error(filename, location.first_line, "Static cast with zero or negative size!\n");

is_signed = sign_hint;

return sig;

}

sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);

RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd));

RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);

int mem_width, mem_size, addr_bits;

is_signed = id2ast->is_signed;

id2ast->meminfo(mem_width, mem_size, addr_bits);

RTLIL::SigSpec addr_sig = children[0]->genRTLIL();

return RTLIL::SigSpec(wire);

}

case AST_MEMINIT:

{

std::stringstream sstr;

int mem_width, mem_size, addr_bits;

id2ast->meminfo(mem_width, mem_size, addr_bits);

SigSpec addr_sig = children[0]->genRTLIL();

cell->setPort(ID::ADDR, addr_sig);

cell->parameters[ID::MEMID] = RTLIL::Const(str);

cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));

cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[str]->width);

cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);

}

break;

else

cellname = str;

RTLIL::Cell *cell = current_module->addCell(cellname, celltype);

for (auto &attr : attributes) {

if (attr.second->type != AST_CONSTANT)

case AST_ASSIGN:

{

RTLIL::SigSpec left = children[0]->genRTLIL();

if (left.has_const()) {

RTLIL::SigSpec new_left, new_right;

for (int i = 0; i < GetSize(left); i++)

{

int port_counter = 0, para_counter = 0;

// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass

cell->set_bool_attribute(ID::module_not_derived);

continue;

}

if (child->type == AST_PARASET) {

IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;

log_file_warning(filename, location.first_line, "Replacing floating point parameter %s.%s = %f with string.\n",

log_file_error(filename, location.first_line, "Parameter %s.%s with non-constant value!\n",

log_id(cell), log_id(paraname));

continue;

}

if (child->type == AST_ARGUMENT) {

RTLIL::SigSpec sig;

if (child->str.size() == 0) {

char buf[100];

snprintf(buf, 100, "$%d", ++port_counter);

}

} break;

case AST_FCALL: {

if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq")

{

log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());

Cell *cell = current_module->addCell(myid, str.substr(1));

cell->parameters[ID::WIDTH] = width;

if (attributes.count(ID::reg)) {

}

Wire *wire = current_module->addWire(myid + "_wire", width);

cell->setPort(ID::Y, wire);

is_signed = sign_hint;

default:

for (auto f : log_files)

current_ast_mod->dumpAst(f, "verilog-ast> ");

}

return RTLIL::SigSpec();

// this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or

// signals must be substituted before being used as input values (used by ProcessGenerator)

// note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().

{

const dict<RTLIL::SigBit, RTLIL::SigBit> *backup_subst_ptr = genRTLIL_subst_ptr;

if (new_subst_ptr)

genRTLIL_subst_ptr = new_subst_ptr;

int width_hint = width;

detectSignWidthWorker(width_hint, sign_hint);

RTLIL::SigSpec sig = genRTLIL(width_hint, sign_hint);

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

case 'S':

case 'd':

case 'D':

goto unsupported_format;

YS_FALLTHROUGH

case 'x':

goto unsupported_format;

break;

default:

unsupported_format:

log_file_error(filename, location.first_line, "System task `%s' called with invalid/unsupported format specifier.\n", str.c_str());

sout += log_id(current_module->name);

break;

default:

log_abort();

}

log_assert(current_scope.count(enum_type) == 1);

AstNode *enum_node = current_scope.at(enum_type);

log_assert(enum_node->type == AST_ENUM);

//get width from 1st enum item:

log_assert(enum_node->children.size() >= 1);

AstNode *enum_item0 = enum_node->children[0];

}

}

// range nodes are now redundant

node->children.clear();

}

else if (node->children.size() == 1 && node->children[0]->type == AST_MULTIRANGE) {

save_struct_array_width(node, width);

width *= array_count;

// range nodes are now redundant

node->children.clear();

}

else if (node->range_left < 0) {

static AstNode *node_int(int ival)

{

}

{

// adjust the range expressions to add an offset into the struct

// and maybe index using an array stride

auto left = left_expr->clone();

auto right = right_expr->clone();

}

else {

}

return new AstNode(AST_RANGE, left, right);

}

{

// Work out the range in the packed array that corresponds to a struct member

// taking into account any range operations applicable to the current node

int range_right = member_node->range_right;

if (node->children.empty()) {

// no range operations apply, return the whole width

}

}

else {

struct_op_error(node);

}

}

static void add_members_to_scope(AstNode *snode, std::string name)

return wnode;

}

// convert the AST into a simpler AST that has all parameters substituted by their

// values, unrolled for-loops, expanded generate blocks, etc. when this function

// is done with an AST it can be converted into RTLIL using genRTLIL().

static bool deep_recursion_warning = false;

if (recursion_counter++ == 1000 && deep_recursion_warning) {

deep_recursion_warning = false;

}

AstNode *newNode = NULL;

bool did_something = false;

// also merge multiple declarations for the same wire (e.g. "output foobar; reg foobar;")

if (type == AST_MODULE) {

current_scope.clear();

std::map<std::string, AstNode*> this_wire_scope;

for (size_t i = 0; i < children.size(); i++) {

AstNode *node = children[i];

}

}

}

}

// create name resolution entries for all objects with names

for (size_t i = 0; i < children.size(); i++) {

AstNode *node = children[i];

// these nodes appear at the top level in a package and can define names

current_scope[node->str] = node;

}

if (node->type == AST_ENUM) {

}

}

int backup_width_hint = width_hint;

bool backup_sign_hint = sign_hint;

if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->id2ast->is_logic)

children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment

if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg)

if (type == AST_ASSIGN && children[0]->id2ast->is_reg) {

bool is_rand_reg = false;

if (children[1]->type == AST_FCALL) {

is_rand_reg = true;

}

if (!is_rand_reg)

}

children[0]->was_checked = true;

}

break;

case AST_TERNARY:

child_0_is_self_determined = true;

break;

detectSignWidth(width_hint, sign_hint);

if (type == AST_TERNARY) {

int width_hint_left, width_hint_right;

bool sign_hint_left, sign_hint_right;

bool found_real_left, found_real_right;

if (const_fold && type == AST_CASE)

{

while (children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { }

if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) {

std::vector<AstNode*> new_children;

new_children.push_back(children[0]);

for (int i = 1; i < GetSize(children); i++) {

continue;

while (v->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { }

if (v->type == AST_CONSTANT && v->bits_only_01()) {

while (i+1 < GetSize(children))

delete children[++i];

goto keep_const_cond;

}

}

// simplify all children first

// (iterate by index as e.g. auto wires can add new children in the process)

for (size_t i = 0; i < children.size(); i++) {

bool did_something_here = true;

bool backup_flag_autowire = flag_autowire;

if ((type == AST_GENFOR || type == AST_FOR) && i >= 3)

break;

if ((type == AST_GENIF || type == AST_GENCASE) && i >= 1)

break;

if (type == AST_DEFPARAM && i == 0)

flag_autowire = true;

while (did_something_here && i < children.size()) {

bool const_fold_here = const_fold, in_lvalue_here = in_lvalue;

int width_hint_here = width_hint;

did_something = true;

}

flag_autowire = backup_flag_autowire;

}

for (auto &attr : attributes) {

while (attr.second->simplify(true, false, false, stage, -1, false, true))

did_something = true;

}

if (reset_width_after_children) {

width_hint = backup_width_hint;

if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) {

// replace with wire representing the packed structure

newNode = make_packed_struct(template_node, str);

current_scope[str] = this;

goto apply_newNode;

}

if (is_custom_type) {

log_assert(children.size() == 2);

log_assert(children[1]->type == AST_WIRETYPE);

if (resolved_type_node->type != AST_TYPEDEF)

log_assert(resolved_type_node->children.size() == 1);

AstNode *template_node = resolved_type_node->children[0];

// Ensure typedef itself is fully simplified

if (template_node->type == AST_MEMORY)

log_file_error(filename, location.first_line, "unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str());

{

int total_size = 1;

multirange_dimensions.clear();

for (auto range : children[1]->children) {

if (!range->range_valid)

log_file_error(filename, location.first_line, "Non-constant range on memory decl.\n");

multirange_dimensions.push_back(min(range->range_left, range->range_right));

multirange_dimensions.push_back(max(range->range_left, range->range_right) - min(range->range_left, range->range_right) + 1);

total_size *= multirange_dimensions.back();

}

delete children[1];

{

AstNode *index_expr = nullptr;

for (int i = 0; 2*i < GetSize(id2ast->multirange_dimensions); i++)

{

log_file_error(filename, location.first_line, "Insufficient number of array indices for %s.\n", log_id(str));

AstNode *new_index_expr = children[0]->children[i]->children.at(0)->clone();

newNode = new AstNode(AST_IDENTIFIER, range);

newNode->str = sname;

newNode->basic_prep = true;

goto apply_newNode;

}

}

if (type == AST_IDENTIFIER) {

if (current_scope.count(str) == 0) {

AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod;

for (auto node : current_scope_ast->children) {

//log("looking at mod scope child %s\n", type2str(node->type).c_str());

switch (node->type) {

}

// split memory access with bit select to individual statements

{

if (id2ast == NULL || id2ast->type != AST_MEMORY || children[0]->children.size() != 1)

log_file_error(filename, location.first_line, "Invalid bit-select on memory access!\n");

newNode = new AstNode(AST_IDENTIFIER, children[1]->clone());

newNode->str = wire_id;

newNode->id2ast = wire;

goto apply_newNode;

}

body_ast->children.size() == 1 && body_ast->children.at(0)->type == AST_GENBLOCK)

body_ast = body_ast->children.at(0);

if (init_ast->type != AST_ASSIGN_EQ)

if (next_ast->type != AST_ASSIGN_EQ)

if (init_ast->children[0]->id2ast != next_ast->children[0]->id2ast)

// eval 1st expression

AstNode *varbuf = init_ast->children[1]->clone();

}

if (varbuf->type != AST_CONSTANT)

auto resolved = current_scope.at(init_ast->children[0]->str);

if (resolved->range_valid) {

}

if (buf->type != AST_CONSTANT)

if (buf->integer == 0) {

delete buf;

// expand body

int index = varbuf->children[0]->integer;

std::stringstream sstr;

sstr << buf->str << "[" << index << "].";

if (type == AST_GENFOR) {

for (size_t i = 0; i < buf->children.size(); i++) {

current_ast_mod->children.push_back(buf->children[i]);

}

} else {

}

if (buf->type != AST_CONSTANT)

delete varbuf->children[0];

varbuf->children[0] = buf;

{

for (size_t i = 0; i < children.size(); i++)

if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF)

}

// transform block with name

if (type == AST_BLOCK && !str.empty())

{

std::vector<AstNode*> new_children;

for (size_t i = 0; i < children.size(); i++)

if (type == AST_GENBLOCK && children.size() != 0)

{

if (!str.empty()) {

}

for (size_t i = 0; i < children.size(); i++) {

current_ast_mod->children.push_back(children[i]);

}

buf = new AstNode(AST_GENBLOCK, buf);

if (!buf->str.empty()) {

}

for (size_t i = 0; i < buf->children.size(); i++) {

current_ast_mod->children.push_back(buf->children[i]);

}

buf = selected_case->clone();

if (!buf->str.empty()) {

}

for (size_t i = 0; i < buf->children.size(); i++) {

current_ast_mod->children.push_back(buf->children[i]);

}

children.push_back(node);

did_something = true;

}

else

{

AstNodeType op_type = AST_NONE;

op_type = AST_BIT_XOR;

if (str == "xnor")

op_type = AST_BIT_XOR, invert_results = true;

log_assert(op_type != AST_NONE);

AstNode *node = children_list[1];

if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)

log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());

result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;

}

bool use_case_method = false;

current_scope[wire_addr->str] = wire_addr;

while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { }

assign_addr->children[0]->str = id_addr;

assign_addr->children[0]->was_checked = true;

defNode->children.push_back(assign_addr);

assign_addr->children[0]->str = id_addr;

assign_addr->children[0]->was_checked = true;

newNode->children.push_back(assign_addr);

current_scope[wire_data->str] = wire_data;

while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }

assign_data->children[0]->str = id_data;

assign_data->children[0]->was_checked = true;

defNode->children.push_back(assign_data);

node_data->str = id_data;

}

if (!defNode->children.empty())

current_top_block->children.insert(current_top_block->children.begin(), defNode);

std::vector<RTLIL::State> padding_x(offset, RTLIL::State::Sx);

new AstNode(AST_CONCAT, mkconst_bits(padding_x, false), children[1]->clone()));

assign_data->children[0]->str = id_data;

assign_data->children[0]->was_checked = true;

}

else

{

log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());

int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;

new AstNode(AST_SHIFT_LEFT, children[1]->clone(), offset_ast->clone()));

assign_data->children[0]->str = id_data;

assign_data->children[0]->was_checked = true;

delete left_at_zero_ast;

delete right_at_zero_ast;

else

{

if (!(children[0]->children.size() == 1 && children[1]->isConst())) {

assign_data->children[0]->str = id_data;

assign_data->children[0]->was_checked = true;

}

}

if (assign_data)

newNode->children.push_back(assign_data);

if (assign_en)

newNode->children.push_back(assign_en);

wrnode->str = children[0]->str;

wrnode->id2ast = children[0]->id2ast;

if (newNode->children.empty()) {

delete newNode;

goto apply_newNode;

}

{

int dim = 1;

}

AstNode *buf = children[0]->clone();

int mem_depth = 1;

AstNode *id_ast = NULL;

// Is this needed?

id_ast = current_scope.at(buf->str);

if (!id_ast)

log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", buf->str.c_str());

if (id_ast->type == AST_MEMORY) {

// We got here only if the argument is a memory

// Otherwise $size() and $bits() return the expression width

} else

log_file_error(filename, location.first_line, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str());

} else {

if (mem_range->type == AST_RANGE) {

dims = GetSize(id_ast->multirange_dimensions)/2;

log_file_error(filename, location.first_line, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str());

}

}

}

delete buf;

goto apply_newNode;

}

goto apply_newNode;

}

if (current_scope.count(str) != 0 && current_scope[str]->type == AST_DPI_FUNCTION)

{

AstNode *dpi_decl = current_scope[str];

log_file_error(filename, location.first_line, "Can't resolve task name `%s'.\n", str.c_str());

}

std::stringstream sstr;

std::string prefix = sstr.str();

{

bool all_args_const = true;

for (auto child : children) {

while (child->simplify(true, false, false, 1, -1, false, true)) { }

all_args_const = false;

}

if (all_args_const) {

delete func_workspace;

}

if (in_param)

}

size_t arg_count = 0;

dict<std::string, AstNode*> wire_cache;

vector<AstNode*> new_stmts;

vector<AstNode*> output_assignments;

log_assert(type == AST_FCALL);

AstNode *wire = NULL;

for (auto child : decl->children)

wire = child->clone();

log_assert(wire != NULL);

wire->port_id = 0;

wire->is_input = false;

wire->is_output = false;

current_ast_mod->children.push_back(wire);

while (wire->simplify(true, false, false, 1, -1, false, false)) { }

if (child->type == AST_WIRE && (child->is_input || child->is_output || (type == AST_FCALL && child->str == str)))

{

AstNode *wire = child->clone();

wire->port_id = 0;

wire->is_input = false;

wire->is_output = false;

if (wire_cache.count(child->str))

{

wire = wire_cache.at(child->str);

for (auto c : child->children)

wire->children.push_back(c->clone());

} else if (!child->children.empty()) {

while (child->simplify(true, false, false, stage, -1, false, false)) { }

for (int i = 0; i < GetSize(child->children); i++)

goto tcall_incompatible_wires;

} else {

tcall_incompatible_wires:

else

{

wire = child->clone();

wire->port_id = 0;

wire->is_input = false;

wire->is_output = false;

wire_cache[child->str] = wire;

current_ast_mod->children.push_back(wire);

}

if ((child->is_input || child->is_output) && arg_count < children.size())

{

AstNode *arg = children[arg_count++]->clone();

AstNode *wire_id = new AstNode(AST_IDENTIFIER);

wire_id->str = wire->str;

AstNode *assign = child->is_input ?

}

}

for (auto child : decl->children)

if (child->type != AST_WIRE && child->type != AST_MEMORY && child->type != AST_PARAMETER && child->type != AST_LOCALPARAM)

new_stmts.insert(new_stmts.end(), output_assignments.begin(), output_assignments.end());

}

replace_fcall_with_id:

if (type == AST_FCALL) {

delete_children();

type = AST_IDENTIFIER;

}

if (type == AST_TCALL)

str = "";

if (current_scope[str]->children[0]->isConst())

newNode = current_scope[str]->children[0]->clone();

}

newNode = mkconst_int(0, sign_hint, width_hint);

}

break;

case AST_TERNARY:

if (children[0]->isConst())

{

if (choice != NULL) {

if (choice->type == AST_CONSTANT) {

case AST_CAST_SIZE:

if (children.at(0)->type == AST_CONSTANT && children.at(1)->type == AST_CONSTANT) {

int width = children[0]->bitsAsConst().as_int();

newNode = mkconst_bits(val.bits, children[1]->is_signed);

}

break;

return did_something;

}

{

}

// replace a readmem[bh] TCALL ast node with a block of memory assignments

AstNode *meminit = nullptr;

int next_meminit_cursor=0;

vector<State> meminit_bits;

int meminit_size=0;

std::ifstream f;

f.open(mem_filename.c_str());

if (f.fail()) {

{

if (meminit != nullptr) {

meminit->children[1] = AstNode::mkconst_bits(meminit_bits, false);

}

meminit = new AstNode(AST_MEMINIT);

meminit->children.push_back(AstNode::mkconst_int(cursor, false));

meminit->children.push_back(nullptr);

meminit->children.push_back(nullptr);

meminit->str = memory->str;

meminit->id2ast = memory;

if (meminit != nullptr) {

meminit->children[1] = AstNode::mkconst_bits(meminit_bits, false);

}

return block;

}

{

}

}

for (size_t i = 0; i < children.size(); i++) {

AstNode *child = children[i];

current_scope[child->str] = child;

for (auto enode : child->children){

log_assert(enode->type == AST_ENUM_ITEM);

}

}

}

for (size_t i = 0; i < children.size(); i++) {

AstNode *child = children[i];

continue;

}

{

}

}

}

log_assert(children[0]->type == AST_CONSTANT);

log_assert(children[1]->type == AST_CONSTANT);

log_assert(children[2]->type == AST_CONSTANT);

int cursor = children[0]->asInt(false);

Const data = children[1]->bitsAsConst();

if (length != 0)

{

int wordsz = GetSize(data) / length;

for (int i = 0; i < length; i++) {

}

}

if (children[0]->children[0]->type == AST_CONSTANT)

{

int id = children[0]->children[0]->integer;

}

else

{

case AST_POSEDGE:

case AST_NEGEDGE:

return false;

case AST_BLOCK:

if (!c->detect_latch(var))

return false;

}

}

{

if (type == AST_WHILE || type == AST_REPEAT)

return true;

for (auto child : children)

return true;

return false;

}

}

// helper function for AstNode::eval_const_function()

{

if (type == AST_IDENTIFIER && variables.count(str)) {

int offset = variables.at(str).offset, width = variables.at(str).val.bits.size();

if (!children.empty()) {

while (simplify(true, false, false, 1, -1, false, true)) { }

offset = min(children.at(0)->range_left, children.at(0)->range_right);

width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width);

}

AstNode *newNode = mkconst_bits(new_bits, variables.at(str).is_signed);

newNode->cloneInto(this);

delete newNode;

}

for (auto &child : children)

}

{

std::map<std::string, AstNode::varinfo_t> variables;

AstNode *block = new AstNode(AST_BLOCK);

size_t argidx = 0;

for (auto child : children)

{

block->children.push_back(child->clone());

}

while (!block->children.empty())

{

AstNode *stmt = block->children.front();

stmt->dumpAst(NULL, "stmt> ");

#endif

if (stmt->type == AST_ASSIGN_EQ)

{

if (stmt->children.at(0)->type == AST_IDENTIFIER && stmt->children.at(0)->children.size() != 0 &&

stmt->children.at(0)->children.at(0)->type == AST_RANGE)

while (stmt->simplify(true, false, false, 1, -1, false, true)) { }

if (stmt->type != AST_ASSIGN_EQ)

continue;

if (stmt->children.at(0)->children.empty()) {

variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size());

} else {

AstNode *range = stmt->children.at(0)->children.at(0);

int offset = min(range->range_left, range->range_right);

int width = std::abs(range->range_left - range->range_right) + 1;

varinfo_t &v = variables[stmt->children.at(0)->str];

if (stmt->type == AST_WHILE)

{

AstNode *cond = stmt->children.at(0)->clone();

while (cond->simplify(true, false, false, 1, -1, false, true)) { }

if (cond->asBool()) {

block->children.insert(block->children.begin(), stmt->children.at(1)->clone());

if (stmt->type == AST_REPEAT)

{

AstNode *num = stmt->children.at(0)->clone();

while (num->simplify(true, false, false, 1, -1, false, true)) { }

block->children.erase(block->children.begin());

for (int i = 0; i < num->bitsAsConst().as_int(); i++)

if (stmt->type == AST_CASE)

{

AstNode *expr = stmt->children.at(0)->clone();

while (expr->simplify(true, false, false, 1, -1, false, true)) { }

AstNode *sel_case = NULL;

for (size_t j = 0; j+1 < stmt->children.at(i)->children.size() && !found_match; j++)

{

AstNode *cond = stmt->children.at(i)->children.at(j)->clone();

cond = new AstNode(AST_EQ, expr->clone(), cond);

while (cond->simplify(true, false, false, 1, -1, false, true)) { }

found_match = cond->asBool();

delete cond;

if (stmt->type == AST_BLOCK)

{

block->children.erase(block->children.begin());

block->children.insert(block->children.begin(), stmt->children.begin(), stmt->children.end());

stmt->children.clear();

continue;

}

log_abort();

}

delete block;

}

void AstNode::allocateDefaultEnumValues()

{

log_assert(type==AST_ENUM);

int last_enum_int = -1;

for (auto node : children) {

log_assert(node->type==AST_ENUM_ITEM);

}

}

YOSYS_NAMESPACE_END

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

for (int i = 0; i+1 < GetSize(name); i++) {

if (name[i] == '[')

pos = i;

pos = -1;

else if (i == pos+1 && name[i] == '0' && name[i+1] != ']')

pos = -1;

}

if (pos >= 0)

failed:

}

void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool run_clean, bool sop_mode, bool wideports)

if (wideports) {

std::pair<RTLIL::IdString, int> wp = wideports_split(p);

wideports_cache[wp.first].second = !strcmp(cmd, ".inputs");

}

}

IdString celltype = RTLIL::escape_id(p);

RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);

dict<RTLIL::IdString, dict<int, SigBit>> cell_wideports_cache;

if (wideports) {

std::pair<RTLIL::IdString, int> wp = wideports_split(p);

cell->setPort(RTLIL::escape_id(p), *q ? blif_wire(q) : SigSpec());

} else {

cell->setPort(RTLIL::escape_id(p), *q ? blif_wire(q) : SigSpec());

}

for (auto &it : cell_wideports_cache)

{

int width = 0;

for (auto &b : it.second)

width = std::max(width, b.first + 1);

SigSpec sig;

for (int i = 0; i < width; i++) {

else

sig.append(module->addWire(NEW_ID));

}

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

break;

}

{

type = 'N';

data_string += ch;

while (1)

data_string += ch;

}

data_string = "";

break;

json_parse_attr_param(cell->parameters, cell_node->data_dict.at("parameters"));

}

}

}

struct JsonFrontend : public Frontend {

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

log(" -> {\"method\": \"derive\", \"module\": \"<module-name\">, \"parameters\": {\n");

log(" \"<param-name>\": {\"type\": \"[unsigned|signed|string|real]\",\n");

log(" \"value\": \"<param-value>\"}, ...}}\n");

log(" <- {\"error\": \"<error-message>\"}\n");

log(" request for the module <module-name> to be derived for a specific set of\n");

log(" parameters. <param-name> starts with \\ for named parameters, and with $\n");

std::string arg = args[argidx];

if (arg == "-exec" && argidx+1 < args.size()) {

command.insert(command.begin(), args.begin() + argidx + 1, args.end());

continue;

}

if (arg == "-path" && argidx+1 < args.size()) {

continue;

}

break;

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

* ---

*

* A very simple and straightforward frontend for the RTLIL text

*

*/

#include "kernel/register.h"

#include "kernel/log.h"

{

}

YOSYS_NAMESPACE_BEGIN

void help() override

{

// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|

log("\n");

log("\n");

log("representation of a design in yosys's internal format.)\n");

log("\n");

log(" -nooverwrite\n");

}

void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override

{

size_t argidx;

for (argidx = 1; argidx < args.size(); argidx++) {

std::string arg = args[argidx];

if (arg == "-nooverwrite") {

continue;

}

if (arg == "-overwrite") {

continue;

}

if (arg == "-lib") {

continue;

}

break;

log("Input filename: %s\n", filename.c_str());

}

} IlangFrontend;

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

* ---

*

* A very simple and straightforward frontend for the RTLIL text

*

*/

#include "kernel/yosys.h"

YOSYS_NAMESPACE_BEGIN

extern std::istream *lexin;

extern RTLIL::Design *current_design;

extern bool flag_nooverwrite;

YOSYS_NAMESPACE_END

#endif

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

* ---

*

* A very simple and straightforward frontend for the RTLIL text

*

*/

#endif

#include <cstdlib>

USING_YOSYS_NAMESPACE

#define YY_INPUT(buf,result,max_size) \

%}

%option yylineno

%option noyywrap

%option nounput

%x STRING

"global" { return TOK_GLOBAL; }

"init" { return TOK_INIT; }

"update" { return TOK_UPDATE; }

"process" { return TOK_PROCESS; }

"end" { return TOK_END; }

[a-z]+ { return TOK_INVALID; }

-?[0-9]+ {

char *end = nullptr;

errno = 0;

return TOK_INVALID; // literal out of range of long

if (value < INT_MIN || value > INT_MAX)

return TOK_INVALID; // literal out of range of int (relevant mostly for LP64 platforms)

return TOK_INT;

}

yystr[j++] = yystr[i++];

}

yystr[j] = 0;

return TOK_STRING;

}

<STRING>. { yymore(); }

%%

// this is a hack to avoid the 'yyinput defined but not used' error msgs

return (void*)&yyinput;

}

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

* ---

*

* A very simple and straightforward frontend for the RTLIL text

*

*/

%{

#include <list>

YOSYS_NAMESPACE_BEGIN

std::istream *lexin;

RTLIL::Design *current_design;

RTLIL::Module *current_module;

bool flag_nooverwrite, flag_overwrite, flag_lib;

bool delete_current_module;

}

YOSYS_NAMESPACE_END

USING_YOSYS_NAMESPACE

%}

/* The union is defined in the header, so we need to provide all the

* includes it requires

%code requires {

#include <string>

#include <vector>

}

%union {

%token TOK_AUTOIDX TOK_MODULE TOK_WIRE TOK_WIDTH TOK_INPUT TOK_OUTPUT TOK_INOUT

%token TOK_CELL TOK_CONNECT TOK_SWITCH TOK_CASE TOK_ASSIGN TOK_SYNC

%token TOK_LOW TOK_HIGH TOK_POSEDGE TOK_NEGEDGE TOK_EDGE TOK_ALWAYS TOK_GLOBAL TOK_INIT

%token TOK_PARAMETER TOK_ATTRIBUTE TOK_MEMORY TOK_SIZE TOK_SIGNED TOK_REAL TOK_UPTO

%type <rsigspec> sigspec_list_reversed

attrbuf.clear();

} design {

if (attrbuf.size() != 0)

};

EOL:

log("Ignoring blackbox re-definition of module %s.\n", $2);

delete_current_module = true;

} else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) {

} else if (flag_nooverwrite) {

log("Ignoring re-definition of module %s.\n", $2);

delete_current_module = true;

free($2);

} module_body TOK_END {

if (attrbuf.size() != 0)

current_module->fixup_ports();

if (delete_current_module)

delete current_module;

TOK_PARAMETER TOK_ID constant EOL {

current_module->avail_parameters($2);

current_module->parameter_default_values[$2] = *$3;

free($2);

};

wire_stmt:

TOK_WIRE {

current_wire->attributes = attrbuf;

attrbuf.clear();

} wire_options TOK_ID EOL {

if (current_module->wire($4) != nullptr)

current_module->rename(current_wire, $4);

free($4);

};

current_wire->width = $3;

} |

wire_options TOK_WIDTH TOK_INVALID {

} |

wire_options TOK_UPTO {

current_wire->upto = true;

attrbuf.clear();

} memory_options TOK_ID EOL {

if (current_module->memories.count($4) != 0)

current_memory->name = $4;

current_module->memories[$4] = current_memory;

free($4);

cell_stmt:

TOK_CELL TOK_ID TOK_ID EOL {

if (current_module->cell($3) != nullptr)

current_cell = current_module->addCell($3, $2);

current_cell->attributes = attrbuf;

attrbuf.clear();

} |

cell_body TOK_CONNECT TOK_ID sigspec EOL {

if (current_cell->hasPort($3))

current_cell->setPort($3, *$4);

delete $4;

free($3);

proc_stmt:

TOK_PROCESS TOK_ID EOL {

if (current_module->processes.count($2) != 0)

current_process->attributes = attrbuf;

switch_stack.clear();

switch_stack.push_back(&current_process->root_case.switches);

case_stack.clear();

assign_stmt:

TOK_ASSIGN sigspec sigspec EOL {

if (attrbuf.size() != 0)

case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3));

delete $2;

delete $3;

delete $3;

delete $4;

} |

/* empty */;

constant:

} |

TOK_ID {

if (current_module->wire($1) == nullptr)

$$ = new RTLIL::SigSpec(current_module->wire($1));

free($1);

} |

sigspec '[' TOK_INT ']' {

if ($3 >= $1->size() || $3 < 0)

$$ = new RTLIL::SigSpec($1->extract($3));

delete $1;

} |

sigspec '[' TOK_INT ':' TOK_INT ']' {

if ($3 >= $1->size() || $3 < 0 || $3 < $5)

$$ = new RTLIL::SigSpec($1->extract($5, $3 - $5 + 1));

delete $1;

} |

conn_stmt:

TOK_CONNECT sigspec sigspec EOL {

if (attrbuf.size() != 0)

current_module->connect(*$2, *$3);

delete $2;

delete $3;

share/verific:

$(P) rm -rf share/verific.new

$(Q) mkdir -p share/verific.new

$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987

$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993

$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008

$(Q) chmod -R a+rX share/verific.new

$(Q) mv share/verific.new share/verific

This directory contains Verific bindings for Yosys.

Verific Features that should be enabled in your Verific library

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

#include "kernel/sigtools.h"

#include "kernel/celltypes.h"

#include "kernel/log.h"

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#endif

#include "veri_file.h"

#include "hier_tree.h"

#include "VeriModule.h"

#include "VeriWrite.h"

#include "VeriLibrary.h"

#endif

#endif

#ifdef __clang__

return;

if (!type_range->IsTypeEnum())

return;

if (nl->IsFromVhdl() && strcmp(type_range->GetTypeName(), "STD_LOGIC") == 0)

return;

auto type_name = type_range->GetTypeName();

if (!type_name)

return;

p = nullptr;

else

for (auto q = p+2; *q != '\0'; q++)

p = nullptr;

break;

}

log_error("Expected TypeRange value '%s' to be of form <decimal>'b<binary>.\n", v);

attributes.emplace(stringf("\\enum_value_%s", p+2), RTLIL::escape_id(k));

}

else if (nl->IsFromVhdl()) {

auto p = v;

if (p) {

auto *q = p+1;

for (; *q != '"'; q++)

if (*q != '0' && *q != '1') {

}

if (p && *(q+1) != '\0')

p = nullptr;

}

}

if (p == nullptr)

}

}

}

}

return true;

}

module->addMuxGate(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));

return true;

}

return true;

}

return false;

}

return true;

}

cell = module->addMux(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));

import_attributes(cell->attributes, inst);

return true;

return true;

}

#define IN operatorInput(inst)

#define IN1 operatorInput1(inst)

#define IN2 operatorInput2(inst)

}

if (inst->Type() == OPER_NTO1MUX) {

import_attributes(cell->attributes, inst);

return true;

}

if (inst->Type() == OPER_WIDE_NTO1MUX)

{

import_attributes(cell->attributes, inst);

return true;

}

return true;

}

#undef IN

#undef IN1

#undef IN2

merge_past_ffs_clock(it.second, it.first.first, it.first.second);

}

void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo, bool norename)

{

std::string netlist_name = nl->GetAtt(" \\top") ? nl->CellBaseName() : nl->Owner()->Name();

module_name += nl->Name();

module_name += ")";

}

}

netlist = nl;

} else {

log("Importing module %s.\n", RTLIL::id2cstr(module->name));

}

SetIter si;

MapIter mi, mi2;

wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());

import_attributes(wire->attributes, portbus, nl);

wire->port_input = true;

if (portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_OUT)

wire->port_output = true;

for (int i = portbus->LeftIndex();; i += portbus->IsUp() ? +1 : -1) {

if (portbus->ElementAtIndex(i) && portbus->ElementAtIndex(i)->GetNet()) {

net = portbus->ElementAtIndex(i)->GetNet();

RTLIL::SigBit bit(wire, i - wire->start_offset);

if (net_map.count(net) == 0)

net_map[net] = bit;

module->connect(net_map_at(net), bit);

else

module->connect(bit, net_map_at(net));

module->memories[memory->name] = memory;

int number_of_bits = net->Size();

int bits_in_word = number_of_bits;

FOREACH_PORTREF_OF_NET(net, si, pr) {

if (pr->GetInst()->Type() == OPER_READ_PORT) {

continue;

}

if (!mode_keep && verific_sva_prims.count(inst->Type())) {

if (verific_verbose)

log(" skipping SVA cell in non k-mode\n");

inst_type += inst->View()->Name();

inst_type += ")";

}

}

RTLIL::Cell *cell = module->addCell(inst_name, inst_type);

{

log_assert(GetSize(sig_d) == GetSize(sig_q));

} else {

w->attributes[ID::init] = init_value;

}

if (enable_sig != State::S1)

sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);

if (disable_sig != State::S0) {

log_assert(GetSize(sig_q) == GetSize(init_value));

return module->addAdff(name, clock_sig, disable_sig, sig_d, sig_q, init_value, posedge);

}

return module->addFf(name, sig_d, sig_q);

return module->addDff(name, clock_sig, sig_d, sig_q, posedge);

}

log_assert(gclk == false);

log_assert(disable_sig == State::S0);

if (enable_sig != State::S1)

sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);

log_assert(gclk == false);

log_assert(disable_sig == State::S0);

if (enable_sig != State::S1)

sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);

return module->addDffsr(name, clock_sig, sig_set, sig_clr, sig_d, sig_q, posedge);

}

// ==================================================================

struct VerificExtNets

std::set<Netlist*> nl_todo, nl_done;

VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1);

Array *netlists = NULL;

Array veri_libs, vhdl_libs;

if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);

if (veri_lib) veri_libs.InsertLast(veri_lib);

Map verific_params(STRING_HASH);

for (const auto &i : parameters)

verific_params.Insert(i.first.c_str(), i.second.c_str());

if (top.empty()) {

netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);

}

}

}

if (vhdl_lib) {

VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str());

if (vhdl_unit)

vhdl_units.InsertLast(vhdl_unit);

}

netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);

}

}

veri_file::Reset();

vhdl_file::Reset();

Libset::Reset();

verific_incdirs.clear();

verific_libdirs.clear();

log("\n");

log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");

log("the language version (and before file names) to set additional verilog defines.\n");

log("\n");

log("\n");

log(" verific -formal <verilog-file>..\n");

log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");

log("\n");

log("\n");

log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");

log("\n");

log("Load the specified VHDL files into Verific.\n");

log("\n");

log("\n");

log(" verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>\n");

log("\n");

log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");

log(" Dump the Verific netlist as a verilog file.\n");

log("\n");

log("\n");

log("\n");

log("\n");

}

#ifdef YOSYS_ENABLE_VERIFIC

if (check_noverific_env())

log_cmd_error("This version of Yosys is built without Verific support.\n"

"\n"

"\n"

log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n");

Message::SetConsoleOutput(0);

Message::RegisterCallBackMsg(msg_func);

RuntimeFlags::SetVar("db_preserve_user_nets", 1);

RuntimeFlags::SetVar("db_allow_external_nets", 1);

RuntimeFlags::SetVar("db_infer_wide_operators", 1);

RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);

RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);

RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);

RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);

RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);

RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);

RuntimeFlags::SetVar("vhdl_preserve_assignments", 1);

// Workaround for VIPER #13851

RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);

// https://github.com/YosysHQ/yosys/issues/1055

RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ;

#ifndef DB_PRESERVE_INITIAL_VALUE

# warning Verific was built without DB_PRESERVE_INITIAL_VALUE.

#endif

break;

}

if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||

args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal"))

{

else

log_abort();

veri_file::DefineMacro("VERIFIC");

veri_file::DefineMacro(args[argidx] == "-formal" ? "FORMAL" : "SYNTHESIS");

while (argidx < GetSize(args))

file_names.Insert(args[argidx++].c_str());

log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");

verific_import_pending = true;

goto check_error;

}

if (GetSize(args) > argidx && args[argidx] == "-vhdl87") {

vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());

for (argidx++; argidx < GetSize(args); argidx++)

verific_import_pending = true;

goto check_error;

}

if (GetSize(args) > argidx && args[argidx] == "-import")

{

std::set<Netlist*> nl_todo, nl_done;

std::set<std::string> top_mod_names;

if (mode_all)

{

log("Running hier_tree::ElaborateAll().\n");

VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);

Array veri_libs, vhdl_libs;

if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);

if (veri_lib) veri_libs.InsertLast(veri_lib);

Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &parameters);

if (argidx == GetSize(args))

cmd_error(args, argidx, "No top module specified.\n");

Array veri_modules, vhdl_units;

for (; argidx < GetSize(args); argidx++)

{

const char *name = args[argidx].c_str();

top_mod_names.insert(name);

}

if (vhdl_unit) {

log("Adding VHDL unit '%s' to elaboration queue.\n", name);

vhdl_units.InsertLast(vhdl_unit);

continue;

}

log_error("Can't find module/unit '%s'.\n", name);

}

log("Running hier_tree::Elaborate().\n");

Array *netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);

Netlist *nl;

}

veri_file::Reset();

vhdl_file::Reset();

Libset::Reset();

verific_incdirs.clear();

verific_libdirs.clear();

goto check_error;

}

cmd_error(args, argidx, "Missing or unsupported mode parameter.\n");

check_error:

void execute(std::vector<std::string>, RTLIL::Design *) override {

log_cmd_error("This version of Yosys is built without Verific support.\n"

"\n"

"\n"

}

#endif

} VerificPass;

log("the language version (and before file names) to set additional verilog defines.\n");

log("\n");

log("\n");

log(" read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");

log("\n");

log("Load the specified VHDL files. (Requires Verific.)\n");

log("\n");

log("\n");

log(" read -define <macro>[=<value>]..\n");

log("\n");

log("Set global Verilog/SystemVerilog defines.\n");

return;

}

if (args[1] == "-vhdl87" || args[1] == "-vhdl93" || args[1] == "-vhdl2k" || args[1] == "-vhdl2008" || args[1] == "-vhdl") {

if (use_verific) {

args[0] = "verific";

}

return;

}

if (args[1] == "-define") {

if (use_verific) {

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

RTLIL::Cell *addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const init_value = Const());

RTLIL::Cell *addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec sig_d, SigSpec sig_q, Const arst_value);

RTLIL::Cell *addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, SigSpec sig_d, SigSpec sig_q);

bool property_matches_sequence(const VerificClocking &seq) const {

if (clock_net != seq.clock_net)

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

[[noreturn]] void parser_error(Instance *inst)

{

}

dict<Net*, bool, hash_ptr_ops> check_expression_cache;

clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0);

}

// generate fair/live cell

RTLIL::Cell *c = nullptr;

frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y

$(Q) mkdir -p $(dir $@)

frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

#include "verilog_frontend.h"

#include "kernel/log.h"

#include <assert.h>

#include <stdarg.h>

#include <stdio.h>

#include <string.h>

return_char(ch);

}

}

else if (ch == '/')

{

if ((ch = next_char()) != 0) {

define_map_t::define_map_t()

{

add("YOSYS", "1");

}

// We must define this destructor here (rather than relying on the default), because we need to

defines[name] = std::unique_ptr<define_body_t>(new define_body_t(txt, args));

}

void define_map_t::merge(const define_map_t &map)

{

for (const auto &pr : map.defines) {

// the argument list); false if we finished with ','.

static bool read_argument(std::string &dest)

{

std::vector<char> openers;

for (;;) {

std::string tok = next_token(true);

if (tok == ")") {

return true;

if (openers.back() != '(')

log_error("Mismatched brackets in macro argument: %c and %c.\n",

openers.back(), tok[0]);

}

}

{

if (tok == "`\"") {

std::string literal("\"");

if (ntok == "`\"") {

insert_input(literal+"\"");

return true;

literal += ntok;

}

}

std::string name = tok.substr(1);

std::string skipped_spaces = skip_spaces();

tok = next_token(false);

std::vector<std::string> args;

bool done = false;

while (!done) {

args.push_back(arg);

}

for (const auto &pr : body->args.get_vals(name, args)) {

defines.add(pr.first, pr.second);

}

} else {

defines.merge(pre_defines);

defines.merge(global_defines_cache);

std::vector<std::string> filename_stack;

int ifdef_fail_level = 0;

output_code.clear();

input_buffer.clear();

if (tok == "`endif") {

if (ifdef_fail_level > 0)

ifdef_fail_level--;

continue;

}

if (tok == "`else") {

ifdef_fail_level = 1;

ifdef_fail_level = 0;

continue;

}

if (tok == "`elsif") {

skip_spaces();

std::string name = next_token(true);

continue;

}

if (tok == "`ifdef") {

skip_spaces();

std::string name = next_token(true);

ifdef_fail_level++;

continue;

}

if (tok == "`ifndef") {

skip_spaces();

std::string name = next_token(true);

ifdef_fail_level++;

continue;

}

if (tok == "`include") {

skip_spaces();

std::string fn = next_token(true);

fn = next_token();

}

while (1) {

continue;

}

continue;

output_code.push_back(tok);

}

std::string output;

for (auto &str : output_code)

output += str;

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

// Add a definition, overwriting any existing definition for name.

void add(const std::string &name, const std::string &txt, const arg_map_t *args = nullptr);

// Merge in another map of definitions (which take precedence

// over anything currently defined).

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

}

}

}

}

struct VerilogFrontend : public Frontend {

log(" enable support for SystemVerilog assertions and some Yosys extensions\n");

log(" replace the implicit -D SYNTHESIS with -D FORMAL\n");

log("\n");

log(" -noassert\n");

log(" ignore assert() statements\n");

log("\n");

log("the syntax of the code, rather than to rely on read_verilog for that.\n");

log("\n");

log("Depending on if read_verilog is run in -formal mode, either the macro\n");

log("\n");

log("See the Yosys README file for a list of non-standard Verilog features\n");

log("supported by the Yosys Verilog front-end.\n");

bool flag_defer = false;

bool flag_noblackbox = false;

bool flag_nowb = false;

define_map_t defines_map;

std::list<std::string> include_dirs;

formal_mode = true;

continue;

}

if (arg == "-noassert") {

noassert_mode = true;

continue;

}

break;

}

extra_args(f, filename, args, argidx);

log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str());

// make package typedefs available to parser

add_package_types(pkg_user_types, design->verilog_packages);

frontend_verilog_yyset_lineno(1);

frontend_verilog_yyrestart(NULL);

frontend_verilog_yyparse();

if (!flag_nopp)

delete lexin;

delete current_ast;

current_ast = NULL;

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

// names of locally typedef'ed types in a stack

typedef std::map<std::string, AST::AstNode*> UserTypeMap;

// names of package typedef'ed types

extern dict<std::string, AST::AstNode*> pkg_user_types;

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

#ifdef __clang__

// bison generates code using the 'register' storage class specifier

#pragma clang diagnostic ignored "-Wdeprecated-register"

#endif

#include "kernel/log.h"

{

// check current scope then outer scopes for a name

for (auto it = user_type_stack.rbegin(); it != user_type_stack.rend(); ++it) {

return true;

}

}

"automatic" { return TOK_AUTOMATIC; }

"unique" { SV_KEYWORD(TOK_UNIQUE); }

"priority" { SV_KEYWORD(TOK_PRIORITY); }

"always_comb" { SV_KEYWORD(TOK_ALWAYS_COMB); }

"const" { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }

"checker" { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); }

"endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }

"final" { SV_KEYWORD(TOK_FINAL); }

"logic" { SV_KEYWORD(TOK_LOGIC); }

"var" { SV_KEYWORD(TOK_VAR); }

"int" { SV_KEYWORD(TOK_INT); }

"byte" { SV_KEYWORD(TOK_BYTE); }

"shortint" { SV_KEYWORD(TOK_SHORTINT); }

"eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }

"s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }

"output" { return TOK_OUTPUT; }

"inout" { return TOK_INOUT; }

"wire" { return TOK_WIRE; }

"wor" { return TOK_WOR; }

"wand" { return TOK_WAND; }

"reg" { return TOK_REG; }

"integer" { return TOK_INTEGER; }

"signed" { return TOK_SIGNED; }

"/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {

static bool printed_warning = false;

if (!printed_warning) {

printed_warning = true;

}

BEGIN(SYNOPSYS_TRANSLATE_OFF);

<SYNOPSYS_FLAGS>full_case {

static bool printed_warning = false;

if (!printed_warning) {

printed_warning = true;

}

return TOK_SYNOPSYS_FULL_CASE;

<SYNOPSYS_FLAGS>parallel_case {

static bool printed_warning = false;

if (!printed_warning) {

printed_warning = true;

}

return TOK_SYNOPSYS_PARALLEL_CASE;

".*" { return TOK_WILDCARD_CONNECT; }

"-=" { SV_KEYWORD(TOK_SUB_ASSIGN); }

[-+]?[=*]> {

if (!specify_mode) REJECT;

/*

* yosys -- Yosys Open SYnthesis Suite

*

*

* Permission to use, copy, modify, and/or distribute this software for any

* purpose with or without fee is hereby granted, provided that the above

*

*/

%{

#include <list>

#include <stack>

dict<IdString, AstNode*> *attr_list, default_attr_list;

std::stack<dict<IdString, AstNode*> *> attr_list_stack;

dict<IdString, AstNode*> *albuf;

dict<std::string, AstNode*> pkg_user_types;

std::vector<AstNode*> ast_stack;

struct AstNode *astbuf1, *astbuf2, *astbuf3;

specify_triple fall;

};

static void addTypedefNode(std::string *name, AstNode *node)

{

log_assert(node);

auto *tnode = new AstNode(AST_TYPEDEF, node);

tnode->str = *name;

if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {

// typedef inside a package so we need the qualified name

auto qname = current_ast_mod->str + "::" + (*name).substr(1);

static void enterTypeScope()

{

}

static void exitTypeScope()

static bool isInLocalScope(const std::string *name)

{

// tests if a name was declared in the current block scope

}

static AstNode *getTypeDefinitionNode(std::string type_name)

{