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-rw-r--r--frontends/ast/ast.cc3
-rw-r--r--frontends/ast/ast.h2
-rw-r--r--frontends/ast/genrtlil.cc18
-rw-r--r--frontends/ast/simplify.cc215
-rw-r--r--frontends/blif/blifparse.cc14
-rw-r--r--frontends/liberty/liberty.cc18
-rw-r--r--frontends/rpc/rpc_frontend.cc12
-rw-r--r--frontends/verific/README2
-rw-r--r--frontends/verific/verific.cc623
-rw-r--r--frontends/verific/verific.h3
-rw-r--r--frontends/verific/verificsva.cc4
-rw-r--r--frontends/verilog/preproc.cc5
-rw-r--r--frontends/verilog/verilog_parser.y13
13 files changed, 700 insertions, 232 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 6097f02f5..982943d1b 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1649,7 +1649,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
AstNode *new_ast = NULL;
std::string modname = derive_common(design, parameters, &new_ast, quiet);
- if (!design->has(modname)) {
+ if (!design->has(modname) && new_ast) {
new_ast->str = modname;
process_module(design, new_ast, false, NULL, quiet);
design->module(modname)->check();
@@ -1699,6 +1699,7 @@ std::string AST::derived_module_name(std::string stripped_name, const std::vecto
std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet)
{
std::string stripped_name = name.str();
+ (*new_ast_out) = nullptr;
if (stripped_name.compare(0, 9, "$abstract") == 0)
stripped_name = stripped_name.substr(9);
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 80497c131..142ec0801 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -203,7 +203,7 @@ namespace AST
// if this is a multirange memory then this vector contains offset and length of each dimension
std::vector<int> multirange_dimensions;
- std::vector<bool> multirange_swapped; // true if range is swapped, not used for structs
+ std::vector<bool> multirange_swapped; // true if range is swapped
// this is set by simplify and used during RTLIL generation
AstNode *id2ast;
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index d81c53dfb..1016ef636 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -45,7 +45,7 @@ using namespace AST_INTERNAL;
// helper function for creating RTLIL code for unary operations
static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
{
- IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
+ IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(that->filename).c_str(), that->location.first_line, autoidx++);
RTLIL::Cell *cell = current_module->addCell(name, type);
set_src_attr(cell, that);
@@ -77,7 +77,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
return;
}
- IdString name = stringf("$extend$%s:%d$%d", that->filename.c_str(), that->location.first_line, autoidx++);
+ IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(that->filename).c_str(), that->location.first_line, autoidx++);
RTLIL::Cell *cell = current_module->addCell(name, ID($pos));
set_src_attr(cell, that);
@@ -104,7 +104,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
// helper function for creating RTLIL code for binary operations
static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
{
- IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
+ IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(that->filename).c_str(), that->location.first_line, autoidx++);
RTLIL::Cell *cell = current_module->addCell(name, type);
set_src_attr(cell, that);
@@ -138,7 +138,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
log_assert(cond.size() == 1);
std::stringstream sstr;
- sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
+ sstr << "$ternary$" << RTLIL::encode_filename(that->filename) << ":" << that->location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux));
set_src_attr(cell, that);
@@ -321,7 +321,7 @@ struct AST_INTERNAL::ProcessGenerator
LookaheadRewriter la_rewriter(always);
// generate process and simple root case
- proc = current_module->addProcess(stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++));
+ proc = current_module->addProcess(stringf("$proc$%s:%d$%d", RTLIL::encode_filename(always->filename).c_str(), always->location.first_line, autoidx++));
set_src_attr(proc, always);
for (auto &attr : always->attributes) {
if (attr.second->type != AST_CONSTANT)
@@ -877,7 +877,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
if (children.size() > 1)
range = children[1];
- } else if (id_ast->type == AST_STRUCT_ITEM || id_ast->type == AST_STRUCT) {
+ } else if (id_ast->type == AST_STRUCT_ITEM || id_ast->type == AST_STRUCT || id_ast->type == AST_UNION) {
AstNode *tmp_range = make_struct_member_range(this, id_ast);
this_width = tmp_range->range_left - tmp_range->range_right + 1;
delete tmp_range;
@@ -1776,7 +1776,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_MEMRD:
{
std::stringstream sstr;
- sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
+ sstr << "$memrd$" << str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd));
set_src_attr(cell, this);
@@ -1814,7 +1814,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_MEMINIT:
{
std::stringstream sstr;
- sstr << "$meminit$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
+ sstr << "$meminit$" << str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
SigSpec en_sig = children[2]->genRTLIL();
@@ -1869,7 +1869,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
IdString cellname;
if (str.empty())
- cellname = stringf("%s$%s:%d$%d", celltype.c_str(), filename.c_str(), location.first_line, autoidx++);
+ cellname = stringf("%s$%s:%d$%d", celltype.c_str(), RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
else
cellname = str;
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 2d9d6dc79..717645183 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -285,10 +285,9 @@ static void save_struct_array_width(AstNode *node, int width)
}
-static int get_struct_array_width(AstNode *node)
+static void save_struct_range_swapped(AstNode *node, bool range_swapped)
{
- // the stride for the array, 1 if not an array
- return (node->multirange_dimensions.empty() ? 1 : node->multirange_dimensions.back());
+ node->multirange_swapped.push_back(range_swapped);
}
@@ -318,38 +317,49 @@ static int size_packed_struct(AstNode *snode, int base_offset)
// member width e.g. bit [7:0] a
width = range_width(node, node->children[0]);
if (node->children.size() == 2) {
+ // Unpacked array. Note that this is a Yosys extension; only packed data types
+ // and integer data types are allowed in packed structs / unions in SystemVerilog.
if (node->children[1]->type == AST_RANGE) {
- // unpacked array e.g. bit [63:0] a [0:3]
+ // Unpacked array, e.g. bit [63:0] a [0:3]
auto rnode = node->children[1];
- int array_count = range_width(node, rnode);
- if (array_count == 1) {
- // C-type array size e.g. bit [63:0] a [4]
- array_count = rnode->range_left;
- }
+ // C-style array size, e.g. bit [63:0] a [4]
+ bool c_type = rnode->children.size() == 1;
+ int array_count = c_type ? rnode->range_left : range_width(node, rnode);
+ save_struct_array_width(node, array_count);
+ save_struct_range_swapped(node, rnode->range_swapped || c_type);
save_struct_array_width(node, width);
+ save_struct_range_swapped(node, node->children[0]->range_swapped);
width *= array_count;
}
else {
- // array element must be single bit for a packed array
+ // The Yosys extension for unpacked arrays in packed structs / unions
+ // only supports memories, i.e. e.g. logic [7:0] a [256] - see above.
struct_array_packing_error(node);
}
+ } else {
+ // Vector
+ save_struct_array_width(node, width);
+ save_struct_range_swapped(node, node->children[0]->range_swapped);
}
// range nodes are now redundant
for (AstNode *child : node->children)
delete child;
node->children.clear();
}
- else if (node->children.size() == 1 && node->children[0]->type == AST_MULTIRANGE) {
- // packed 2D array, e.g. bit [3:0][63:0] a
- auto rnode = node->children[0];
- if (rnode->children.size() != 2) {
- // packed arrays can only be 2D
+ else if (node->children.size() > 0 && node->children[0]->type == AST_MULTIRANGE) {
+ // Packed array, e.g. bit [3:0][63:0] a
+ if (node->children.size() != 1) {
+ // The Yosys extension for unpacked arrays in packed structs / unions
+ // only supports memories, i.e. e.g. logic [7:0] a [256] - see above.
struct_array_packing_error(node);
}
- int array_count = range_width(node, rnode->children[0]);
- width = range_width(node, rnode->children[1]);
- save_struct_array_width(node, width);
- width *= array_count;
+ width = 1;
+ for (auto rnode : node->children[0]->children) {
+ int rwidth = range_width(node, rnode);
+ save_struct_array_width(node, rwidth);
+ save_struct_range_swapped(node, rnode->range_swapped);
+ width *= rwidth;
+ }
// range nodes are now redundant
for (AstNode *child : node->children)
delete child;
@@ -408,55 +418,51 @@ static AstNode *multiply_by_const(AstNode *expr_node, int stride)
return new AstNode(AST_MUL, expr_node, node_int(stride));
}
-static AstNode *offset_indexed_range(int offset, int stride, AstNode *left_expr, AstNode *right_expr)
+static AstNode *normalize_struct_index(AstNode *expr, AstNode *member_node, int dimension)
{
- // adjust the range expressions to add an offset into the struct
- // and maybe index using an array stride
- auto left = left_expr->clone();
- auto right = right_expr->clone();
- if (stride > 1) {
- // newleft = (left + 1) * stride - 1
- left = new AstNode(AST_SUB, multiply_by_const(new AstNode(AST_ADD, left, node_int(1)), stride), node_int(1));
- // newright = right * stride
- right = multiply_by_const(right, stride);
- }
- // add the offset
- if (offset) {
- left = new AstNode(AST_ADD, node_int(offset), left);
- right = new AstNode(AST_ADD, node_int(offset), right);
+ expr = expr->clone();
+
+ if (member_node->multirange_swapped[dimension]) {
+ // The dimension has swapped range; swap index into the struct accordingly.
+ int msb = member_node->multirange_dimensions[dimension] - 1;
+ expr = new AstNode(AST_SUB, node_int(msb), expr);
}
- return new AstNode(AST_RANGE, left, right);
+
+ return expr;
}
-static AstNode *make_struct_index_range(AstNode *node, AstNode *rnode, int stride, int offset)
+static AstNode *struct_index_lsb_offset(AstNode *lsb_offset, AstNode *rnode, AstNode *member_node, int dimension, int &stride)
{
- // generate a range node to perform either bit or array indexing
+ stride /= member_node->multirange_dimensions[dimension];
+ auto right = normalize_struct_index(rnode->children.back(), member_node, dimension);
+ auto offset = stride > 1 ? multiply_by_const(right, stride) : right;
+ return new AstNode(AST_ADD, lsb_offset, offset);
+}
+
+static AstNode *struct_index_msb_offset(AstNode *lsb_offset, AstNode *rnode, AstNode *member_node, int dimension, int stride)
+{
+ log_assert(rnode->children.size() <= 2);
+
+ // Offset to add to LSB
+ AstNode *offset;
if (rnode->children.size() == 1) {
- // index e.g. s.a[i]
- return offset_indexed_range(offset, stride, rnode->children[0], rnode->children[0]);
- }
- else if (rnode->children.size() == 2) {
- // slice e.g. s.a[i:j]
- return offset_indexed_range(offset, stride, rnode->children[0], rnode->children[1]);
+ // Index, e.g. s.a[i]
+ offset = node_int(stride - 1);
}
else {
- struct_op_error(node);
+ // rnode->children.size() == 2
+ // Slice, e.g. s.a[i:j]
+ auto left = normalize_struct_index(rnode->children[0], member_node, dimension);
+ auto right = normalize_struct_index(rnode->children[1], member_node, dimension);
+ offset = new AstNode(AST_SUB, left, right);
+ if (stride > 1) {
+ // offset = (msb - lsb + 1)*stride - 1
+ auto slice_width = new AstNode(AST_ADD, offset, node_int(1));
+ offset = new AstNode(AST_SUB, multiply_by_const(slice_width, stride), node_int(1));
+ }
}
-}
-static AstNode *slice_range(AstNode *rnode, AstNode *snode)
-{
- // apply the bit slice indicated by snode to the range rnode
- log_assert(rnode->type==AST_RANGE);
- auto left = rnode->children[0];
- auto right = rnode->children[1];
- log_assert(snode->type==AST_RANGE);
- auto slice_left = snode->children[0];
- auto slice_right = snode->children[1];
- auto width = new AstNode(AST_SUB, slice_left->clone(), slice_right->clone());
- right = new AstNode(AST_ADD, right->clone(), slice_right->clone());
- left = new AstNode(AST_ADD, right->clone(), width);
- return new AstNode(AST_RANGE, left, right);
+ return new AstNode(AST_ADD, lsb_offset, offset);
}
@@ -471,24 +477,38 @@ AstNode *AST::make_struct_member_range(AstNode *node, AstNode *member_node)
// no range operations apply, return the whole width
return make_range(range_left, range_right);
}
- int stride = get_struct_array_width(member_node);
- if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
- // bit or array indexing e.g. s.a[2] or s.a[1:0]
- return make_struct_index_range(node, node->children[0], stride, range_right);
+
+ if (node->children.size() != 1) {
+ struct_op_error(node);
}
- else if (node->children.size() == 1 && node->children[0]->type == AST_MULTIRANGE) {
- // multirange, i.e. bit slice after array index, e.g. s.a[i][p:q]
- log_assert(stride > 1);
- auto mrnode = node->children[0];
- auto element_range = make_struct_index_range(node, mrnode->children[0], stride, range_right);
- // then apply bit slice range
- auto range = slice_range(element_range, mrnode->children[1]);
- delete element_range;
- return range;
+
+ // Range operations
+ auto rnode = node->children[0];
+ auto lsb_offset = node_int(member_node->range_right);
+ int stride = range_left - range_right + 1;
+ size_t i = 0;
+
+ // Calculate LSB offset for the final index / slice
+ if (rnode->type == AST_RANGE) {
+ lsb_offset = struct_index_lsb_offset(lsb_offset, rnode, member_node, i, stride);
+ }
+ else if (rnode->type == AST_MULTIRANGE) {
+ // Add offset for each dimension
+ auto mrnode = rnode;
+ for (i = 0; i < mrnode->children.size(); i++) {
+ rnode = mrnode->children[i];
+ lsb_offset = struct_index_lsb_offset(lsb_offset, rnode, member_node, i, stride);
+ }
+ i--; // Step back to the final index / slice
}
else {
struct_op_error(node);
}
+
+ // Calculate MSB offset for the final index / slice
+ auto msb_offset = struct_index_msb_offset(lsb_offset->clone(), rnode, member_node, i, stride);
+
+ return new AstNode(AST_RANGE, msb_offset, lsb_offset);
}
static void add_members_to_scope(AstNode *snode, std::string name)
@@ -996,7 +1016,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
// create name resolution entries for all objects with names
// also merge multiple declarations for the same wire (e.g. "output foobar; reg foobar;")
- if (type == AST_MODULE) {
+ if (type == AST_MODULE || type == AST_INTERFACE) {
current_scope.clear();
std::set<std::string> existing;
int counter = 0;
@@ -1240,7 +1260,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
// create the indirection wire
std::stringstream sstr;
- sstr << "$indirect$" << ref->name.c_str() << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
+ sstr << "$indirect$" << ref->name.c_str() << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
std::string tmp_str = sstr.str();
add_wire_for_ref(ref, tmp_str);
@@ -1587,6 +1607,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
break;
if (type == AST_GENBLOCK)
break;
+ if (type == AST_CELLARRAY && children[i]->type == AST_CELL)
+ continue;
if (type == AST_BLOCK && !str.empty())
break;
if (type == AST_PREFIX && i >= 1)
@@ -1679,7 +1701,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
current_filename = filename;
- if (type == AST_MODULE)
+ if (type == AST_MODULE || type == AST_INTERFACE)
current_scope.clear();
// convert defparam nodes to cell parameters
@@ -2041,7 +2063,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (name_has_dot(str, sname)) {
if (current_scope.count(str) > 0) {
auto item_node = current_scope[str];
- if (item_node->type == AST_STRUCT_ITEM || item_node->type == AST_STRUCT) {
+ if (item_node->type == AST_STRUCT_ITEM || item_node->type == AST_STRUCT || item_node->type == AST_UNION) {
// structure member, rewrite this node to reference the packed struct wire
auto range = make_struct_member_range(this, item_node);
newNode = new AstNode(AST_IDENTIFIER, range);
@@ -2127,7 +2149,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
std::swap(data_range_left, data_range_right);
std::stringstream sstr;
- sstr << "$mem2bits$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
+ sstr << "$mem2bits$" << str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
std::string wire_id = sstr.str();
AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true)));
@@ -2714,14 +2736,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
// mask and shift operations, disabled for now
AstNode *wire_mask = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
- wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
+ wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
wire_mask->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
wire_mask->is_logic = true;
while (wire_mask->simplify(true, false, false, 1, -1, false, false)) { }
current_ast_mod->children.push_back(wire_mask);
AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
- wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
+ wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
wire_data->is_logic = true;
while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
@@ -2732,7 +2754,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
shift_expr->detectSignWidth(shamt_width_hint, shamt_sign_hint);
AstNode *wire_sel = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(shamt_width_hint-1, true), mkconst_int(0, true)));
- wire_sel->str = stringf("$bitselwrite$sel$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
+ wire_sel->str = stringf("$bitselwrite$sel$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
wire_sel->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
wire_sel->is_logic = true;
wire_sel->is_signed = shamt_sign_hint;
@@ -2809,7 +2831,7 @@ skip_dynamic_range_lvalue_expansion:;
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && current_block != NULL)
{
std::stringstream sstr;
- sstr << "$formal$" << filename << ":" << location.first_line << "$" << (autoidx++);
+ sstr << "$formal$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
std::string id_check = sstr.str() + "_CHECK", id_en = sstr.str() + "_EN";
AstNode *wire_check = new AstNode(AST_WIRE);
@@ -2918,7 +2940,7 @@ skip_dynamic_range_lvalue_expansion:;
newNode = new AstNode(AST_BLOCK);
AstNode *wire_tmp = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(width_hint-1, true), mkconst_int(0, true)));
- wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
+ wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
current_ast_mod->children.push_back(wire_tmp);
current_scope[wire_tmp->str] = wire_tmp;
wire_tmp->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
@@ -2956,7 +2978,7 @@ skip_dynamic_range_lvalue_expansion:;
(children[0]->children.size() == 1 || children[0]->children.size() == 2) && children[0]->children[0]->type == AST_RANGE)
{
std::stringstream sstr;
- sstr << "$memwr$" << children[0]->str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
+ sstr << "$memwr$" << children[0]->str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN";
int mem_width, mem_size, addr_bits;
@@ -3228,7 +3250,7 @@ skip_dynamic_range_lvalue_expansion:;
AstNode *reg = new AstNode(AST_WIRE, new AstNode(AST_RANGE,
mkconst_int(width_hint-1, true), mkconst_int(0, true)));
- reg->str = stringf("$past$%s:%d$%d$%d", filename.c_str(), location.first_line, myidx, i);
+ reg->str = stringf("$past$%s:%d$%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, myidx, i);
reg->is_reg = true;
reg->is_signed = sign_hint;
@@ -3656,6 +3678,8 @@ skip_dynamic_range_lvalue_expansion:;
goto apply_newNode;
}
+ if (current_scope.count(str) == 0)
+ str = try_pop_module_prefix();
if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION)
log_file_error(filename, location.first_line, "Can't resolve function name `%s'.\n", str.c_str());
}
@@ -3727,13 +3751,15 @@ skip_dynamic_range_lvalue_expansion:;
goto apply_newNode;
}
+ if (current_scope.count(str) == 0)
+ str = try_pop_module_prefix();
if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK)
log_file_error(filename, location.first_line, "Can't resolve task name `%s'.\n", str.c_str());
}
std::stringstream sstr;
- sstr << str << "$func$" << filename << ":" << location.first_line << "$" << (autoidx++) << '.';
+ sstr << str << "$func$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++) << '.';
std::string prefix = sstr.str();
AstNode *decl = current_scope[str];
@@ -4586,7 +4612,7 @@ static void mark_memories_assign_lhs_complex(dict<AstNode*, pool<std::string>> &
if (that->type == AST_IDENTIFIER && that->id2ast && that->id2ast->type == AST_MEMORY) {
AstNode *mem = that->id2ast;
if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_CMPLX_LHS))
- mem2reg_places[mem].insert(stringf("%s:%d", that->filename.c_str(), that->location.first_line));
+ mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(that->filename).c_str(), that->location.first_line));
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CMPLX_LHS;
}
}
@@ -4614,14 +4640,14 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
// activate mem2reg if this is assigned in an async proc
if (flags & AstNode::MEM2REG_FL_ASYNC) {
if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ASYNC))
- mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line));
+ mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ASYNC;
}
// remember if this is assigned blocking (=)
if (type == AST_ASSIGN_EQ) {
if (!(proc_flags[mem] & AstNode::MEM2REG_FL_EQ1))
- mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line));
+ mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
proc_flags[mem] |= AstNode::MEM2REG_FL_EQ1;
}
@@ -4638,11 +4664,11 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
// remember where this is
if (flags & MEM2REG_FL_INIT) {
if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_INIT))
- mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line));
+ mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_INIT;
} else {
if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ELSE))
- mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line));
+ mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ELSE;
}
}
@@ -4656,7 +4682,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
// flag if used after blocking assignment (in same proc)
if ((proc_flags[mem] & AstNode::MEM2REG_FL_EQ1) && !(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_EQ2)) {
- mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line));
+ mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line));
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_EQ2;
}
}
@@ -4665,7 +4691,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !(is_reg || is_logic)))
mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
- if (type == AST_MODULE && get_bool_attribute(ID::mem2reg))
+ if ((type == AST_MODULE || type == AST_INTERFACE) && get_bool_attribute(ID::mem2reg))
children_flags |= AstNode::MEM2REG_FL_ALL;
dict<AstNode*, uint32_t> *proc_flags_p = NULL;
@@ -4679,8 +4705,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
children_flags |= AstNode::MEM2REG_FL_ASYNC;
proc_flags_p = new dict<AstNode*, uint32_t>;
}
-
- if (type == AST_INITIAL) {
+ else if (type == AST_INITIAL) {
children_flags |= AstNode::MEM2REG_FL_INIT;
proc_flags_p = new dict<AstNode*, uint32_t>;
}
@@ -4846,7 +4871,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
children[0]->children[0]->children[0]->type != AST_CONSTANT)
{
std::stringstream sstr;
- sstr << "$mem2reg_wr$" << children[0]->str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
+ sstr << "$mem2reg_wr$" << children[0]->str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
int mem_width, mem_size, addr_bits;
@@ -4962,7 +4987,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
else
{
std::stringstream sstr;
- sstr << "$mem2reg_rd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
+ sstr << "$mem2reg_rd$" << str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++);
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA";
int mem_width, mem_size, addr_bits;
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index 19844bda6..ebbe082a2 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -21,6 +21,8 @@
YOSYS_NAMESPACE_BEGIN
+const int lut_input_plane_limit = 12;
+
static bool read_next_line(char *&buffer, size_t &buffer_size, int &line_count, std::istream &f)
{
string strbuf;
@@ -166,7 +168,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
goto error;
module = new RTLIL::Module;
lastcell = nullptr;
- module->name = RTLIL::escape_id(strtok(NULL, " \t\r\n"));
+ char *name = strtok(NULL, " \t\r\n");
+ if (name == nullptr)
+ goto error;
+ module->name = RTLIL::escape_id(name);
obj_attributes = &module->attributes;
obj_parameters = nullptr;
if (design->module(module->name))
@@ -510,6 +515,11 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
sopmode = -1;
lastcell = sopcell;
}
+ else if (input_sig.size() > lut_input_plane_limit)
+ {
+ err_reason = stringf("names' input plane must have fewer than %d signals.", lut_input_plane_limit + 1);
+ goto error_with_reason;
+ }
else
{
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
@@ -573,7 +583,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (lutptr)
{
- if (input_len > 12)
+ if (input_len > lut_input_plane_limit)
goto error;
for (int i = 0; i < (1 << input_len); i++) {
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index abf8de4d1..cadbcaee6 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -464,6 +464,9 @@ struct LibertyFrontend : public Frontend {
log(" -lib\n");
log(" only create empty blackbox modules\n");
log("\n");
+ log(" -wb\n");
+ log(" mark imported cells as whiteboxes\n");
+ log("\n");
log(" -nooverwrite\n");
log(" ignore re-definitions of modules. (the default behavior is to\n");
log(" create an error message if the existing module is not a blackbox\n");
@@ -489,6 +492,7 @@ struct LibertyFrontend : public Frontend {
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_lib = false;
+ bool flag_wb = false;
bool flag_nooverwrite = false;
bool flag_overwrite = false;
bool flag_ignore_miss_func = false;
@@ -496,8 +500,6 @@ struct LibertyFrontend : public Frontend {
bool flag_ignore_miss_data_latch = false;
std::vector<std::string> attributes;
- log_header(design, "Executing Liberty frontend.\n");
-
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
@@ -505,6 +507,10 @@ struct LibertyFrontend : public Frontend {
flag_lib = true;
continue;
}
+ if (arg == "-wb") {
+ flag_wb = true;
+ continue;
+ }
if (arg == "-ignore_redef" || arg == "-nooverwrite") {
flag_nooverwrite = true;
flag_overwrite = false;
@@ -535,6 +541,11 @@ struct LibertyFrontend : public Frontend {
}
extra_args(f, filename, args, argidx);
+ if (flag_wb && flag_lib)
+ log_error("-wb and -lib cannot be specified together!\n");
+
+ log_header(design, "Executing Liberty frontend: %s\n", filename.c_str());
+
LibertyParser parser(*f);
int cell_count = 0;
@@ -572,6 +583,9 @@ struct LibertyFrontend : public Frontend {
if (flag_lib)
module->set_bool_attribute(ID::blackbox);
+ if (flag_wb)
+ module->set_bool_attribute(ID::whitebox);
+
for (auto &attr : attributes)
module->attributes[attr] = 1;
diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc
index c12640ef0..ec3952661 100644
--- a/frontends/rpc/rpc_frontend.cc
+++ b/frontends/rpc/rpc_frontend.cc
@@ -383,12 +383,12 @@ struct RpcFrontend : public Pass {
log(" request for the module <module-name> to be derived for a specific set of\n");
log(" parameters. <param-name> starts with \\ for named parameters, and with $\n");
log(" for unnamed parameters, which are numbered starting at 1.<param-value>\n");
- log(" for integer parameters is always specified as a binary string of unlimited\n");
- log(" precision. the <source> returned by the frontend is hygienically parsed\n");
- log(" by a built-in Yosys <frontend>, allowing the RPC frontend to return any\n");
- log(" convenient representation of the module. the derived module is cached,\n");
- log(" so the response should be the same whenever the same set of parameters\n");
- log(" is provided.\n");
+ log(" for integer parameters is always specified as a binary string of\n");
+ log(" unlimited precision. the <source> returned by the frontend is\n");
+ log(" hygienically parsedby a built-in Yosys <frontend>, allowing the RPC\n");
+ log(" frontend to return anyconvenient representation of the module. the\n");
+ log(" derived module is cached,so the response should be the same whenever the\n");
+ log(" same set of parameters is provided.\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
diff --git a/frontends/verific/README b/frontends/verific/README
index 952fb1e0c..921873af3 100644
--- a/frontends/verific/README
+++ b/frontends/verific/README
@@ -1,7 +1,7 @@
This directory contains Verific bindings for Yosys.
-Use Tabby CAD Suite from YosysHQ if you need Yosys+Verifc.
+Use Tabby CAD Suite from YosysHQ if you need Yosys+Verific.
https://www.yosyshq.com/
Contact YosysHQ at contact@yosyshq.com for free evaluation
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 5e610c0f3..c1e9fc7d0 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -47,20 +47,27 @@ USING_YOSYS_NAMESPACE
#include "VeriModule.h"
#include "VeriWrite.h"
#include "VeriLibrary.h"
+#include "VeriExpression.h"
#ifdef VERIFIC_VHDL_SUPPORT
#include "vhdl_file.h"
#include "VhdlUnits.h"
#endif
+#ifdef VERIFIC_EDIF_SUPPORT
+#include "edif_file.h"
+#endif
+
+#ifdef VERIFIC_LIBERTY_SUPPORT
+#include "synlib_file.h"
+#include "SynlibGroup.h"
+#endif
+
#include "VerificStream.h"
#include "FileSystem.h"
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-#include "InitialAssertions.h"
-#include "VerificBasePass.h"
-#include "TemplateGenerator.h"
-#include "FormalApplication.h"
+#include "VerificExtensions.h"
#endif
#ifndef YOSYSHQ_VERIFIC_API_VERSION
@@ -152,7 +159,7 @@ public:
}
};
-static YosysStreamCallBackHandler stream_cb;
+YosysStreamCallBackHandler verific_read_cb;
// ==================================================================
@@ -188,11 +195,41 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
{
std::string s = stringf("$verific$%s", obj->Name());
if (obj->Linefile())
- s += stringf("$%s:%d", Verific::LineFile::GetFileName(obj->Linefile()), Verific::LineFile::GetLineNo(obj->Linefile()));
+ s += stringf("$%s:%d", RTLIL::encode_filename(Verific::LineFile::GetFileName(obj->Linefile())).c_str(), Verific::LineFile::GetLineNo(obj->Linefile()));
s += stringf("$%d", autoidx++);
return s;
}
+static bool isNumber(const string& str)
+{
+ for (auto &c : str) {
+ if (std::isdigit(c) == 0) return false;
+ }
+ return true;
+}
+
+// When used as attributes or parameter values Verific constants come already processed.
+// - Real string values are already under quotes
+// - Numeric values with specified width are always converted to binary
+// - Rest of user defined values are handled as 32bit integers
+// - There could be some internal values that are strings without quotes
+// so we check if value is all digits or not
+//
+static const RTLIL::Const verific_const(const char *value)
+{
+ std::string val = std::string(value);
+ if (val.size()>1 && val[0]=='\"' && val.back()=='\"')
+ return RTLIL::Const(val.substr(1,val.size()-2));
+ else
+ if (val.find("'b") != std::string::npos)
+ return RTLIL::Const::from_string(val.substr(val.find("'b") + 2));
+ else
+ if (isNumber(val))
+ return RTLIL::Const(std::stoi(val),32);
+ else
+ return RTLIL::Const(val);
+}
+
void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl)
{
MapIter mi;
@@ -201,14 +238,10 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
if (obj->Linefile())
attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
- // FIXME: Parse numeric attributes
FOREACH_ATTRIBUTE(obj, mi, attr) {
if (attr->Key()[0] == ' ' || attr->Value() == nullptr)
continue;
- std::string val = std::string(attr->Value());
- if (val.size()>1 && val[0]=='\"' && val.back()=='\"')
- val = val.substr(1,val.size()-2);
- attributes[RTLIL::escape_id(attr->Key())] = RTLIL::Const(val);
+ attributes[RTLIL::escape_id(attr->Key())] = verific_const(attr->Value());
}
if (nl) {
@@ -328,10 +361,16 @@ RTLIL::SigSpec VerificImporter::operatorInport(Instance *inst, const char *portn
for (unsigned i = 0; i < portbus->Size(); i++) {
Net *net = inst->GetNet(portbus->ElementAtIndex(i));
if (net) {
- if (net->IsGnd())
- sig.append(RTLIL::State::S0);
- else if (net->IsPwr())
- sig.append(RTLIL::State::S1);
+ if (net->IsConstant()) {
+ if (net->IsGnd())
+ sig.append(RTLIL::State::S0);
+ else if (net->IsPwr())
+ sig.append(RTLIL::State::S1);
+ else if (net->IsX())
+ sig.append(RTLIL::State::Sx);
+ else
+ sig.append(RTLIL::State::Sz);
+ }
else
sig.append(net_map_at(net));
} else
@@ -346,6 +385,36 @@ RTLIL::SigSpec VerificImporter::operatorInport(Instance *inst, const char *portn
}
}
+RTLIL::SigSpec VerificImporter::operatorInportCase(Instance *inst, const char *portname)
+{
+ PortBus *portbus = inst->View()->GetPortBus(portname);
+ if (portbus) {
+ RTLIL::SigSpec sig;
+ for (unsigned i = 0; i < portbus->Size(); i++) {
+ Net *net = inst->GetNet(portbus->ElementAtIndex(i));
+ if (net) {
+ if (net->IsConstant()) {
+ if (net->IsGnd())
+ sig.append(RTLIL::State::S0);
+ else if (net->IsPwr())
+ sig.append(RTLIL::State::S1);
+ else
+ sig.append(RTLIL::State::Sa);
+ }
+ else
+ sig.append(net_map_at(net));
+ } else
+ sig.append(RTLIL::State::Sa);
+ }
+ return sig;
+ } else {
+ Port *port = inst->View()->GetPort(portname);
+ log_assert(port != NULL);
+ Net *net = inst->GetNet(port);
+ return net_map_at(net);
+ }
+}
+
RTLIL::SigSpec VerificImporter::operatorOutput(Instance *inst, const pool<Net*, hash_ptr_ops> *any_all_nets)
{
RTLIL::SigSpec sig;
@@ -956,6 +1025,47 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
return true;
}
+ if (inst->Type() == OPER_WIDE_CASE_SELECT_BOX)
+ {
+ RTLIL::SigSpec sig_out_val = operatorInport(inst, "out_value");
+ RTLIL::SigSpec sig_select = operatorInport(inst, "select");
+ RTLIL::SigSpec sig_select_values = operatorInportCase(inst, "select_values");
+ RTLIL::SigSpec sig_data_values = operatorInport(inst, "data_values");
+ RTLIL::SigSpec sig_data_default = operatorInport(inst, "default_value");
+
+ RTLIL::Process *proc = module->addProcess(new_verific_id(inst));
+ import_attributes(proc->attributes, inst);
+
+ RTLIL::CaseRule *current_case = &proc->root_case;
+ current_case = &proc->root_case;
+
+ RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
+ sw->signal = sig_select;
+ current_case->switches.push_back(sw);
+
+ int select_width = inst->InputSize();
+ int data_width = inst->OutputSize();
+ int select_num = inst->Input1Size() / inst->InputSize();
+
+ int offset_select = 0;
+ int offset_data = 0;
+
+ for (int i = 0; i < select_num; i++) {
+ RTLIL::CaseRule *cs = new RTLIL::CaseRule;
+ cs->compare.push_back(sig_select_values.extract(offset_select, select_width));
+ cs->actions.push_back(SigSig(sig_out_val, sig_data_values.extract(offset_data, data_width)));
+ sw->cases.push_back(cs);
+
+ offset_select += select_width;
+ offset_data += data_width;
+ }
+ RTLIL::CaseRule *cs_default = new RTLIL::CaseRule;
+ cs_default->actions.push_back(SigSig(sig_out_val, sig_data_default));
+ sw->cases.push_back(cs_default);
+
+ return true;
+ }
+
#undef IN
#undef IN1
#undef IN2
@@ -1092,6 +1202,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
NetBus *netbus;
Instance *inst;
PortRef *pr;
+ Att *attr;
+
+ FOREACH_ATTRIBUTE(nl, mi, attr) {
+ if (!strcmp(attr->Key(), "noblackbox"))
+ module->set_bool_attribute(ID::blackbox, false);
+ }
FOREACH_PORT_OF_NETLIST(nl, mi, port)
{
@@ -1129,6 +1245,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
RTLIL::Wire *wire = module->addWire(RTLIL::escape_id(portbus->Name()), portbus->Size());
wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
+ wire->upto = portbus->IsUp();
import_attributes(wire->attributes, portbus, nl);
bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN;
@@ -1149,7 +1266,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
wire->port_output = true;
}
net = portbus->ElementAtIndex(i)->GetNet();
- RTLIL::SigBit bit(wire, i - wire->start_offset);
+ int bitidx = wire->upto ? (wire->width - 1 - (i - wire->start_offset)) : (i - wire->start_offset);
+ RTLIL::SigBit bit(wire, bitidx);
if (net_map.count(net) == 0)
net_map[net] = bit;
else if (bit_input)
@@ -1177,6 +1295,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
memory->name = RTLIL::escape_id(net->Name());
log_assert(module->count_id(memory->name) == 0);
module->memories[memory->name] = memory;
+ import_attributes(memory->attributes, net, nl);
int number_of_bits = net->Size();
int bits_in_word = number_of_bits;
@@ -1313,6 +1432,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex());
+ wire->upto = netbus->IsUp();
MapIter mibus;
FOREACH_NET_OF_NETBUS(netbus, mibus, net) {
if (net)
@@ -1327,7 +1447,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
{
if (netbus->ElementAtIndex(i))
{
- int bitidx = i - wire->start_offset;
+ int bitidx = wire->upto ? (wire->width - 1 - (i - wire->start_offset)) : (i - wire->start_offset);
net = netbus->ElementAtIndex(i);
RTLIL::SigBit bit(wire, bitidx);
@@ -2231,7 +2351,7 @@ struct VerificExtNets
}
};
-void verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top)
+std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top)
{
verific_sva_fsm_limit = 16;
@@ -2251,7 +2371,8 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
verific_params.Insert(i.first.c_str(), i.second.c_str());
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
- InitialAssertions::Rewrite("work", &verific_params);
+ VerificExtensions::ElaborateAndRewrite("work", &verific_params);
+ verific_error_msg.clear();
#endif
if (top.empty()) {
@@ -2264,6 +2385,18 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1);
if (veri_module) {
veri_modules.InsertLast(veri_module);
+ if (veri_module->IsConfiguration()) {
+ VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
+ VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast();
+ VeriLibrary *lib = veri_module->GetLibrary() ;
+ if (module_name && module_name->IsHierName()) {
+ VeriName *prefix = module_name->GetPrefix() ;
+ const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
+ if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
+ }
+ if (lib && module_name)
+ top = lib->GetModule(module_name->GetName(), 1)->GetName();
+ }
}
// Also elaborate all root modules since they may contain bind statements
@@ -2288,6 +2421,7 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
int i;
FOREACH_ARRAY_ITEM(netlists, i, nl) {
+ if (!nl) continue;
if (!top.empty() && nl->CellBaseName() != top)
continue;
nl->AddAtt(new Att(" \\top", NULL));
@@ -2317,11 +2451,20 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
nl_todo.erase(it);
}
+#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
+ VerificExtensions::Reset();
+#endif
hier_tree::DeleteHierarchicalTree();
veri_file::Reset();
#ifdef VERIFIC_VHDL_SUPPORT
vhdl_file::Reset();
#endif
+#ifdef VERIFIC_EDIF_SUPPORT
+ edif_file::Reset();
+#endif
+#ifdef VERIFIC_LIBERTY_SUPPORT
+ synlib_file::Reset();
+#endif
Libset::Reset();
Message::Reset();
RuntimeFlags::DeleteAllFlags();
@@ -2333,6 +2476,7 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg.c_str());
+ return top;
}
YOSYS_NAMESPACE_END
@@ -2350,64 +2494,6 @@ bool check_noverific_env()
return false;
return true;
}
-
-void set_verific_global_flags()
-{
- static bool g_set_verific_global_flags = true;
-
- if (g_set_verific_global_flags)
- {
- Message::SetConsoleOutput(0);
- Message::RegisterCallBackMsg(msg_func);
-
- RuntimeFlags::SetVar("db_preserve_user_instances", 1);
- RuntimeFlags::SetVar("db_preserve_user_nets", 1);
- RuntimeFlags::SetVar("db_preserve_x", 1);
-
- RuntimeFlags::SetVar("db_allow_external_nets", 1);
- RuntimeFlags::SetVar("db_infer_wide_operators", 1);
- RuntimeFlags::SetVar("db_infer_set_reset_registers", 0);
-
- RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
- RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
- RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
-
-#ifdef VERIFIC_VHDL_SUPPORT
- RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
- RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
- RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1);
-
- RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
- RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
-
- RuntimeFlags::SetVar("vhdl_preserve_assignments", 1);
- //RuntimeFlags::SetVar("vhdl_preserve_comments", 1);
- RuntimeFlags::SetVar("vhdl_preserve_drivers", 1);
-#endif
- RuntimeFlags::SetVar("veri_preserve_assignments", 1);
- RuntimeFlags::SetVar("veri_preserve_comments", 1);
- RuntimeFlags::SetVar("veri_preserve_drivers", 1);
-
- // Workaround for VIPER #13851
- RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
-
- // WARNING: instantiating unknown module 'XYZ' (VERI-1063)
- Message::SetMessageType("VERI-1063", VERIFIC_ERROR);
-
- // https://github.com/YosysHQ/yosys/issues/1055
- RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ;
-
- RuntimeFlags::SetVar("verific_produce_verbose_syntax_error_message", 1);
-
-#ifndef DB_PRESERVE_INITIAL_VALUE
-# warning Verific was built without DB_PRESERVE_INITIAL_VALUE.
-#endif
-
- veri_file::RegisterCallBackVerificStream(&stream_cb);
-
- g_set_verific_global_flags = false;
- }
-}
#endif
struct VerificPass : public Pass {
@@ -2441,6 +2527,25 @@ struct VerificPass : public Pass {
log("\n");
log("\n");
#endif
+#ifdef VERIFIC_EDIF_SUPPORT
+ log(" verific {-edif} <edif-file>..\n");
+ log("\n");
+ log("Load the specified EDIF files into Verific.\n");
+ log("\n");
+ log("\n");
+#endif
+#ifdef VERIFIC_LIBERTY_SUPPORT
+ log(" verific {-liberty} <liberty-file>..\n");
+ log("\n");
+ log("Load the specified Liberty files into Verific.\n");
+ log("Default library when -work is not present is one specified in liberty file.\n");
+ log("To use from SystemVerilog or VHDL use -L to specify liberty library.");
+ log("\n");
+ log(" -lib\n");
+ log(" only create empty blackbox modules\n");
+ log("\n");
+ log("\n");
+#endif
log(" verific {-f|-F} [-vlog95|-vlog2k|-sv2005|-sv2009|\n");
log(" -sv2012|-sv|-formal] <command-file>\n");
log("\n");
@@ -2519,12 +2624,14 @@ struct VerificPass : public Pass {
log("\n");
log("Set message severity. <msg_id> is the string in square brackets when a message\n");
log("is printed, such as VERI-1209.\n");
+ log("Also errors, warnings, infos and comments could be used to set new severity for\n");
+ log("all messages of certain type.\n");
log("\n");
log("\n");
- log(" verific -import [options] <top-module>..\n");
+ log(" verific -import [options] <top>..\n");
log("\n");
- log("Elaborate the design for the specified top modules, import to Yosys and\n");
- log("reset the internal state of Verific.\n");
+ log("Elaborate the design for the specified top modules or configurations, import to\n");
+ log("Yosys and reset the internal state of Verific.\n");
log("\n");
log("Import options:\n");
log("\n");
@@ -2547,6 +2654,10 @@ struct VerificPass : public Pass {
log(" -fullinit\n");
log(" Keep all register initializations, even those for non-FF registers.\n");
log("\n");
+ log(" -cells\n");
+ log(" Import all cell definitions from Verific loaded libraries even if they are\n");
+ log(" unused in design. Useful with \"-edif\" and \"-liberty\" option.\n");
+ log("\n");
log(" -chparam name value \n");
log(" Elaborate the specified top modules (all modules when -all given) using\n");
log(" this parameter value. Modules on which this parameter does not exist will\n");
@@ -2557,6 +2668,9 @@ struct VerificPass : public Pass {
log(" -v, -vv\n");
log(" Verbose log messages. (-vv is even more verbose than -v.)\n");
log("\n");
+ log(" -pp <filename>\n");
+ log(" Pretty print design after elaboration to specified file.\n");
+ log("\n");
log("The following additional import options are useful for debugging the Verific\n");
log("bindings (for Yosys and/or Verific developers):\n");
log("\n");
@@ -2602,6 +2716,9 @@ struct VerificPass : public Pass {
log("Get/set Verific runtime flags.\n");
log("\n");
log("\n");
+#if defined(YOSYS_ENABLE_VERIFIC) and defined(YOSYSHQ_VERIFIC_EXTENSIONS)
+ VerificExtensions::Help();
+#endif
log("Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n");
log("https://www.yosyshq.com/\n");
log("\n");
@@ -2610,8 +2727,49 @@ struct VerificPass : public Pass {
log("\n");
}
#ifdef YOSYS_ENABLE_VERIFIC
+ std::string frontent_rewrite(std::vector<std::string> &args, int &argidx, std::vector<std::string> &tmp_files)
+ {
+ std::string filename = args[argidx++];
+ //Accommodate heredocs with EOT marker spaced out from "<<", e.g. "<< EOT" vs. "<<EOT"
+ if (filename == "<<" && (argidx < GetSize(args))) {
+ filename += args[argidx++];
+ }
+ if (filename.compare(0, 2, "<<") == 0) {
+ if (filename.size() <= 2)
+ log_error("Missing EOT marker in here document!\n");
+ std::string eot_marker = filename.substr(2);
+ if (Frontend::current_script_file == nullptr)
+ filename = "<stdin>";
+ std::string last_here_document;
+ while (1) {
+ std::string buffer;
+ char block[4096];
+ while (1) {
+ if (fgets(block, 4096, Frontend::current_script_file == nullptr? stdin : Frontend::current_script_file) == nullptr)
+ log_error("Unexpected end of file in here document '%s'!\n", filename.c_str());
+ buffer += block;
+ if (buffer.size() > 0 && (buffer[buffer.size() - 1] == '\n' || buffer[buffer.size() - 1] == '\r'))
+ break;
+ }
+ size_t indent = buffer.find_first_not_of(" \t\r\n");
+ if (indent != std::string::npos && buffer.compare(indent, eot_marker.size(), eot_marker) == 0)
+ break;
+ last_here_document += buffer;
+ }
+ filename = make_temp_file();
+ tmp_files.push_back(filename);
+ std::ofstream file(filename);
+ file << last_here_document;
+ } else {
+ rewrite_filename(filename);
+ }
+ return filename;
+ }
+
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
+ static bool set_verific_global_flags = true;
+
if (check_noverific_env())
log_cmd_error("This version of Yosys is built without Verific support.\n"
"\n"
@@ -2623,7 +2781,56 @@ struct VerificPass : public Pass {
log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n");
- set_verific_global_flags();
+ if (set_verific_global_flags)
+ {
+ Message::SetConsoleOutput(0);
+ Message::RegisterCallBackMsg(msg_func);
+
+ RuntimeFlags::SetVar("db_preserve_user_instances", 1);
+ RuntimeFlags::SetVar("db_preserve_user_nets", 1);
+ RuntimeFlags::SetVar("db_preserve_x", 1);
+
+ RuntimeFlags::SetVar("db_allow_external_nets", 1);
+ RuntimeFlags::SetVar("db_infer_wide_operators", 1);
+ RuntimeFlags::SetVar("db_infer_set_reset_registers", 0);
+
+ RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
+ RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
+ RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
+
+#ifdef VERIFIC_VHDL_SUPPORT
+ RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
+ RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
+ RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1);
+
+ RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
+ RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
+
+ RuntimeFlags::SetVar("vhdl_preserve_assignments", 1);
+ //RuntimeFlags::SetVar("vhdl_preserve_comments", 1);
+ RuntimeFlags::SetVar("vhdl_preserve_drivers", 1);
+#endif
+ RuntimeFlags::SetVar("veri_preserve_assignments", 1);
+ RuntimeFlags::SetVar("veri_preserve_comments", 1);
+ RuntimeFlags::SetVar("veri_preserve_drivers", 1);
+
+ // Workaround for VIPER #13851
+ RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
+
+ // WARNING: instantiating unknown module 'XYZ' (VERI-1063)
+ Message::SetMessageType("VERI-1063", VERIFIC_ERROR);
+
+ // https://github.com/YosysHQ/yosys/issues/1055
+ RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ;
+
+ RuntimeFlags::SetVar("verific_produce_verbose_syntax_error_message", 1);
+
+#ifndef DB_PRESERVE_INITIAL_VALUE
+# warning Verific was built without DB_PRESERVE_INITIAL_VALUE.
+#endif
+
+ set_verific_global_flags = false;
+ }
verific_verbose = 0;
verific_sva_fsm_limit = 16;
@@ -2631,6 +2838,7 @@ struct VerificPass : public Pass {
const char *release_str = Message::ReleaseString();
time_t release_time = Message::ReleaseDate();
char *release_tmstr = ctime(&release_time);
+ std::vector<std::string> tmp_files;
if (release_str == nullptr)
release_str = "(no release string)";
@@ -2642,6 +2850,8 @@ struct VerificPass : public Pass {
int argidx = 1;
std::string work = "work";
+ bool is_work_set = false;
+ veri_file::RegisterCallBackVerificStream(&verific_read_cb);
if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" ||
args[argidx] == "-set-info" || args[argidx] == "-set-ignore"))
@@ -2659,9 +2869,20 @@ struct VerificPass : public Pass {
else
log_abort();
- for (argidx++; argidx < GetSize(args); argidx++)
- Message::SetMessageType(args[argidx].c_str(), new_type);
-
+ for (argidx++; argidx < GetSize(args); argidx++) {
+ if (Strings::compare(args[argidx].c_str(), "errors")) {
+ Message::SetMessageType("VERI-1063", new_type);
+ Message::SetAllMessageType(VERIFIC_ERROR, new_type);
+ } else if (Strings::compare(args[argidx].c_str(), "warnings")) {
+ Message::SetAllMessageType(VERIFIC_WARNING, new_type);
+ } else if (Strings::compare(args[argidx].c_str(), "infos")) {
+ Message::SetAllMessageType(VERIFIC_INFO, new_type);
+ } else if (Strings::compare(args[argidx].c_str(), "comments")) {
+ Message::SetAllMessageType(VERIFIC_COMMENT, new_type);
+ } else {
+ Message::SetMessageType(args[argidx].c_str(), new_type);
+ }
+ }
goto check_error;
}
@@ -2707,10 +2928,25 @@ struct VerificPass : public Pass {
}
veri_file::RemoveAllLOptions();
+ veri_file::AddLOption("work");
+ for (int i = argidx; i < GetSize(args); i++)
+ {
+ if (args[i] == "-work" && i+1 < GetSize(args)) {
+ ++i;
+ continue;
+ }
+ if (args[i] == "-L" && i+1 < GetSize(args)) {
+ if (args[++i] == "work")
+ veri_file::RemoveAllLOptions();
+ continue;
+ }
+ break;
+ }
for (; argidx < GetSize(args); argidx++)
{
if (args[argidx] == "-work" && argidx+1 < GetSize(args)) {
work = args[++argidx];
+ is_work_set = true;
continue;
}
if (args[argidx] == "-L" && argidx+1 < GetSize(args)) {
@@ -2826,9 +3062,10 @@ struct VerificPass : public Pass {
for (auto &ext : verific_libexts)
veri_file::AddLibExt(ext.c_str());
- while (argidx < GetSize(args))
- file_names.Insert(args[argidx++].c_str());
-
+ while (argidx < GetSize(args)) {
+ std::string filename = frontent_rewrite(args, argidx, tmp_files);
+ file_names.Insert(strdup(filename.c_str()));
+ }
if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
verific_error_msg.clear();
log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
@@ -2841,41 +3078,100 @@ struct VerificPass : public Pass {
#ifdef VERIFIC_VHDL_SUPPORT
if (GetSize(args) > argidx && args[argidx] == "-vhdl87") {
vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
- for (argidx++; argidx < GetSize(args); argidx++)
- if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_87))
- log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str());
+ argidx++;
+ while (argidx < GetSize(args)) {
+ std::string filename = frontent_rewrite(args, argidx, tmp_files);
+ if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_87))
+ log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", filename.c_str());
+ }
verific_import_pending = true;
goto check_error;
}
if (GetSize(args) > argidx && args[argidx] == "-vhdl93") {
vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
- for (argidx++; argidx < GetSize(args); argidx++)
- if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_93))
- log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str());
+ argidx++;
+ while (argidx < GetSize(args)) {
+ std::string filename = frontent_rewrite(args, argidx, tmp_files);
+ if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_93))
+ log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", filename.c_str());
+ }
verific_import_pending = true;
goto check_error;
}
if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") {
vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
- for (argidx++; argidx < GetSize(args); argidx++)
- if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2K))
- log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str());
+ argidx++;
+ while (argidx < GetSize(args)) {
+ std::string filename = frontent_rewrite(args, argidx, tmp_files);
+ if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2K))
+ log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", filename.c_str());
+ }
verific_import_pending = true;
goto check_error;
}
if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) {
vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
- for (argidx++; argidx < GetSize(args); argidx++)
- if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2008))
- log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str());
+ argidx++;
+ while (argidx < GetSize(args)) {
+ std::string filename = frontent_rewrite(args, argidx, tmp_files);
+ if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2008))
+ log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", filename.c_str());
+ }
verific_import_pending = true;
goto check_error;
}
#endif
+#ifdef VERIFIC_EDIF_SUPPORT
+ if (GetSize(args) > argidx && args[argidx] == "-edif") {
+ edif_file edif;
+ argidx++;
+ while (argidx < GetSize(args)) {
+ std::string filename = frontent_rewrite(args, argidx, tmp_files);
+ if (!edif.Read(filename.c_str()))
+ log_cmd_error("Reading `%s' in EDIF mode failed.\n", filename.c_str());
+ }
+ goto check_error;
+ }
+#endif
+#ifdef VERIFIC_LIBERTY_SUPPORT
+ if (GetSize(args) > argidx && args[argidx] == "-liberty") {
+ bool flag_lib = false;
+ for (argidx++; argidx < GetSize(args); argidx++) {
+ if (args[argidx] == "-lib") {
+ flag_lib = true;
+ continue;
+ }
+ if (args[argidx].compare(0, 1, "-") == 0) {
+ cmd_error(args, argidx, "unknown option");
+ goto check_error;
+ }
+ break;
+ }
+ while (argidx < GetSize(args)) {
+ std::string filename = frontent_rewrite(args, argidx, tmp_files);
+ if (!synlib_file::Read(filename.c_str(), is_work_set ? work.c_str() : nullptr))
+ log_cmd_error("Reading `%s' in LIBERTY mode failed.\n", filename.c_str());
+ SynlibLibrary *lib = synlib_file::GetLastLibraryAnalyzed();
+ if (lib && flag_lib) {
+ MapIter mi ;
+ Verific::Cell *c ;
+ FOREACH_CELL_OF_LIBRARY(lib->GetLibrary(),mi,c) {
+ MapIter ni ;
+ Netlist *nl;
+ FOREACH_NETLIST_OF_CELL(c, ni, nl) {
+ if (nl)
+ nl->MakeBlackBox();
+ }
+ }
+ }
+ }
+ goto check_error;
+ }
+#endif
if (argidx < GetSize(args) && args[argidx] == "-pp")
{
const char* filename = nullptr;
@@ -2930,8 +3226,9 @@ struct VerificPass : public Pass {
bool mode_all = false, mode_gates = false, mode_keep = false;
bool mode_nosva = false, mode_names = false, mode_verific = false;
bool mode_autocover = false, mode_fullinit = false;
- bool flatten = false, extnets = false;
+ bool flatten = false, extnets = false, mode_cells = false;
string dumpfile;
+ string ppfile;
Map parameters(STRING_HASH);
for (argidx++; argidx < GetSize(args); argidx++) {
@@ -2975,6 +3272,10 @@ struct VerificPass : public Pass {
mode_fullinit = true;
continue;
}
+ if (args[argidx] == "-cells") {
+ mode_cells = true;
+ continue;
+ }
if (args[argidx] == "-chparam" && argidx+2 < GetSize(args)) {
const std::string &key = args[++argidx];
const std::string &value = args[++argidx];
@@ -3000,6 +3301,10 @@ struct VerificPass : public Pass {
dumpfile = args[++argidx];
continue;
}
+ if (args[argidx] == "-pp" && argidx+1 < GetSize(args)) {
+ ppfile = args[++argidx];
+ continue;
+ }
break;
}
@@ -3009,8 +3314,12 @@ struct VerificPass : public Pass {
std::set<std::string> top_mod_names;
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
- InitialAssertions::Rewrite(work, &parameters);
+ VerificExtensions::ElaborateAndRewrite(work, &parameters);
+ verific_error_msg.clear();
#endif
+ if (!ppfile.empty())
+ veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
+
if (mode_all)
{
log("Running hier_tree::ElaborateAll().\n");
@@ -3050,8 +3359,29 @@ struct VerificPass : public Pass {
VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
if (veri_module) {
- log("Adding Verilog module '%s' to elaboration queue.\n", name);
- veri_modules.InsertLast(veri_module);
+ if (veri_module->IsConfiguration()) {
+ log("Adding Verilog configuration '%s' to elaboration queue.\n", name);
+ veri_modules.InsertLast(veri_module);
+
+ top_mod_names.erase(name);
+
+ VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
+ VeriName *module_name;
+ int i;
+ FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) {
+ VeriLibrary *lib = veri_module->GetLibrary() ;
+ if (module_name && module_name->IsHierName()) {
+ VeriName *prefix = module_name->GetPrefix() ;
+ const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
+ if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
+ }
+ if (lib && module_name)
+ top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName());
+ }
+ } else {
+ log("Adding Verilog module '%s' to elaboration queue.\n", name);
+ veri_modules.InsertLast(veri_module);
+ }
continue;
}
#ifdef VERIFIC_VHDL_SUPPORT
@@ -3081,6 +3411,7 @@ struct VerificPass : public Pass {
int i;
FOREACH_ARRAY_ITEM(netlists, i, nl) {
+ if (!nl) continue;
if (!top_mod_names.count(nl->CellBaseName()))
continue;
nl->AddAtt(new Att(" \\top", NULL));
@@ -3088,6 +3419,28 @@ struct VerificPass : public Pass {
}
delete netlists;
}
+ if (mode_cells) {
+ log("Importing all cells.\n");
+ Libset *gls = Libset::Global() ;
+ MapIter it ;
+ Library *l ;
+ FOREACH_LIBRARY_OF_LIBSET(gls,it,l) {
+ MapIter mi ;
+ Verific::Cell *c ;
+ FOREACH_CELL_OF_LIBRARY(l,mi,c) {
+ if (!mode_verific && (l == Library::Primitives() || l == Library::Operators())) continue;
+ MapIter ni ;
+ if (c->NumOfNetlists() == 1) {
+ c->GetFirstNetlist()->SetName("");
+ }
+ Netlist *nl;
+ FOREACH_NETLIST_OF_CELL(c, ni, nl) {
+ if (nl)
+ nl_todo.emplace(nl->CellBaseName(), nl);
+ }
+ }
+ }
+ }
if (!verific_error_msg.empty())
goto check_error;
@@ -3123,11 +3476,20 @@ struct VerificPass : public Pass {
nl_todo.erase(it);
}
+#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
+ VerificExtensions::Reset();
+#endif
hier_tree::DeleteHierarchicalTree();
veri_file::Reset();
#ifdef VERIFIC_VHDL_SUPPORT
vhdl_file::Reset();
#endif
+#ifdef VERIFIC_EDIF_SUPPORT
+ edif_file::Reset();
+#endif
+#ifdef VERIFIC_LIBERTY_SUPPORT
+ synlib_file::Reset();
+#endif
Libset::Reset();
Message::Reset();
RuntimeFlags::DeleteAllFlags();
@@ -3197,10 +3559,24 @@ struct VerificPass : public Pass {
}
}
}
+#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
+ if (VerificExtensions::Execute(args, argidx, work,
+ [this](const std::vector<std::string> &args, size_t argidx, std::string msg)
+ { cmd_error(args, argidx, msg); } )) {
+ goto check_error;
+ }
+#endif
cmd_error(args, argidx, "Missing or unsupported mode parameter.\n");
check_error:
+ if (tmp_files.size()) {
+ log("Removing temp files.\n");
+ for(auto &fn : tmp_files) {
+ remove(fn.c_str());
+ }
+ }
+
if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg.c_str());
@@ -3218,12 +3594,6 @@ struct VerificPass : public Pass {
#endif
} VerificPass;
-
-#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
-VERIFIC_PASS(VerificTemplateGenerator, "template", "generate template")
-VERIFIC_PASS(VerificFormalApplication, "formal_app", "running formal application")
-#endif
-
struct ReadPass : public Pass {
ReadPass() : Pass("read", "load HDL designs") { }
void help() override
@@ -3246,6 +3616,21 @@ struct ReadPass : public Pass {
log("\n");
log("\n");
#endif
+#ifdef VERIFIC_EDIF_SUPPORT
+ log(" read {-edif} <edif-file>..\n");
+ log("\n");
+ log("Load the specified EDIF files. (Requires Verific.)\n");
+ log("\n");
+ log("\n");
+#endif
+ log(" read {-liberty} <liberty-file>..\n");
+ log("\n");
+ log("Load the specified Liberty files.\n");
+ log("\n");
+ log(" -lib\n");
+ log(" only create empty blackbox modules\n");
+ log("\n");
+ log("\n");
log(" read {-f|-F} <command-file>\n");
log("\n");
log("Load and execute the specified command file. (Requires Verific.)\n");
@@ -3339,6 +3724,26 @@ struct ReadPass : public Pass {
return;
}
#endif
+#ifdef VERIFIC_EDIF_SUPPORT
+ if (args[1] == "-edif") {
+ if (use_verific) {
+ args[0] = "verific";
+ Pass::call(design, args);
+ } else {
+ cmd_error(args, 1, "This version of Yosys is built without Verific support.\n");
+ }
+ return;
+ }
+#endif
+ if (args[1] == "-liberty") {
+ if (use_verific) {
+ args[0] = "verific";
+ } else {
+ args[0] = "read_liberty";
+ }
+ Pass::call(design, args);
+ return;
+ }
if (args[1] == "-f" || args[1] == "-F") {
if (use_verific) {
args[0] = "verific";
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h
index 695c04f3b..44485751c 100644
--- a/frontends/verific/verific.h
+++ b/frontends/verific/verific.h
@@ -26,7 +26,7 @@ YOSYS_NAMESPACE_BEGIN
extern int verific_verbose;
extern bool verific_import_pending;
-extern void verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top = std::string());
+extern std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top = std::string());
extern pool<int> verific_sva_prims;
@@ -87,6 +87,7 @@ struct VerificImporter
RTLIL::SigSpec operatorInput1(Verific::Instance *inst);
RTLIL::SigSpec operatorInput2(Verific::Instance *inst);
RTLIL::SigSpec operatorInport(Verific::Instance *inst, const char *portname);
+ RTLIL::SigSpec operatorInportCase(Verific::Instance *inst, const char *portname);
RTLIL::SigSpec operatorOutput(Verific::Instance *inst, const pool<Verific::Net*, hash_ptr_ops> *any_all_nets = nullptr);
bool import_netlist_instance_gates(Verific::Instance *inst, RTLIL::IdString inst_name);
diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index 12bac2a3d..986a98643 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -1777,7 +1777,7 @@ struct VerificSvaImporter
if (mode_assert) c = module->addLive(root_name, sig_a_q, sig_en_q);
if (mode_assume) c = module->addFair(root_name, sig_a_q, sig_en_q);
- importer->import_attributes(c->attributes, root);
+ if (c) importer->import_attributes(c->attributes, root);
return;
}
@@ -1822,7 +1822,7 @@ struct VerificSvaImporter
if (mode_assume) c = module->addAssume(root_name, sig_a_q, sig_en_q);
if (mode_cover) c = module->addCover(root_name, sig_a_q, sig_en_q);
- importer->import_attributes(c->attributes, root);
+ if (c) importer->import_attributes(c->attributes, root);
}
}
catch (ParserErrorException)
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 883531e78..e33b0a2c3 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -961,6 +961,11 @@ frontend_verilog_preproc(std::istream &f,
}
if (tok == "`resetall") {
+ default_nettype_wire = true;
+ continue;
+ }
+
+ if (tok == "`undefineall" && sv_mode) {
defines.clear();
global_defines_cache.clear();
continue;
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index c533b0c40..87b50438a 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -173,6 +173,13 @@ static bool isInLocalScope(const std::string *name)
static AstNode *getTypeDefinitionNode(std::string type_name)
{
+ // check package types
+ if (type_name.find("::") != std::string::npos && pkg_user_types.count(type_name) > 0) {
+ auto typedef_node = pkg_user_types[type_name];
+ log_assert(typedef_node->type == AST_TYPEDEF);
+ return typedef_node->children[0];
+ }
+
// check current scope then outer scopes for a name
for (auto it = user_type_stack.rbegin(); it != user_type_stack.rend(); ++it) {
if (it->count(type_name) > 0) {
@@ -229,9 +236,9 @@ static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
static void rewriteRange(AstNode *rangeNode)
{
if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
- // SV array size [n], rewrite as [n-1:0]
- rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
- rangeNode->children.push_back(AstNode::mkconst_int(0, false));
+ // SV array size [n], rewrite as [0:n-1]
+ rangeNode->children.push_back(new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true)));
+ rangeNode->children[0] = AstNode::mkconst_int(0, false);
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 03:48:12 +0000