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-rw-r--r--frontends/aiger/aigerparse.cc249
-rw-r--r--frontends/aiger/aigerparse.h9
-rw-r--r--frontends/ast/genrtlil.cc9
3 files changed, 236 insertions, 31 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 7df28fe87..56bffcf38 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -26,12 +26,15 @@
#include "kernel/sigtools.h"
#include "aigerparse.h"
+#include <boost/endian/buffers.hpp>
+#include <boost/lexical_cast.hpp>
+
YOSYS_NAMESPACE_BEGIN
#define log_debug log
-AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name)
- : design(design), f(f), clk_name(clk_name)
+AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports)
+ : design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports)
{
module = new RTLIL::Module;
module->name = module_name;
@@ -68,9 +71,9 @@ void AigerReader::parse_aiger()
line_count = 1;
if (header == "aag")
- parse_aiger_ascii();
+ parse_aiger_ascii(true /* create_and */);
else if (header == "aig")
- parse_aiger_binary();
+ parse_aiger_binary(true /* create_and */);
else
log_abort();
@@ -112,6 +115,186 @@ void AigerReader::parse_aiger()
design->add(module);
}
+static uint32_t parse_xaiger_literal(std::istream &f)
+{
+ boost::endian::big_uint32_buf_t l;
+ if (f.readsome(reinterpret_cast<char*>(&l), sizeof(l)) != sizeof(l))
+ log_error("Offset %ld: unable to read literal!\n", boost::lexical_cast<int64_t>(f.tellg()));
+ return l.value();
+}
+
+void AigerReader::parse_xaiger()
+{
+ std::string header;
+ f >> header;
+ if (header != "aag" && header != "aig")
+ log_error("Unsupported AIGER file!\n");
+
+ // Parse rest of header
+ if (!(f >> M >> I >> L >> O >> A))
+ log_error("Invalid AIGER header\n");
+
+ // Optional values
+ B = C = J = F = 0;
+
+ std::string line;
+ std::getline(f, line); // Ignore up to start of next line, as standard
+ // says anything that follows could be used for
+ // optional sections
+
+ log_debug("M=%u I=%u L=%u O=%u A=%u\n", M, I, L, O, A);
+
+ line_count = 1;
+
+ if (header == "aag")
+ parse_aiger_ascii(false /* create_and */);
+ else if (header == "aig")
+ parse_aiger_binary(false /* create_and */);
+ else
+ log_abort();
+
+ // Parse footer (symbol table, comments, etc.)
+ unsigned l1;
+ std::string s;
+ bool comment_seen = false;
+ for (int c = f.peek(); c != EOF; c = f.peek()) {
+ if (comment_seen || c == 'c') {
+ if (!comment_seen) {
+ f.ignore(1);
+ c = f.peek();
+ if (c == '\n')
+ break;
+ f.ignore(1);
+ comment_seen = true;
+ }
+ // XAIGER extensions
+ if (c == 'm') {
+ uint32_t dataSize = parse_xaiger_literal(f);
+ uint32_t lutNum = parse_xaiger_literal(f);
+ uint32_t lutSize = parse_xaiger_literal(f);
+ log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
+ for (unsigned i = 0; i < lutNum; ++i) {
+ uint32_t rootNodeID = parse_xaiger_literal(f);
+ uint32_t cutLeavesM = parse_xaiger_literal(f);
+ log_debug("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
+ RTLIL::Wire *output_sig = module->wire(stringf("\\n%d", rootNodeID));
+ log_assert(output_sig);
+ uint32_t nodeID;
+ RTLIL::SigSpec input_sig;
+ for (unsigned j = 0; j < cutLeavesM; ++j) {
+ nodeID = parse_xaiger_literal(f);
+ log_debug("\t%u\n", nodeID);
+ RTLIL::Wire *wire = module->wire(stringf("\\n%d", nodeID));
+ log_assert(wire);
+ input_sig.append(wire);
+ }
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
+ cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
+ cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
+ cell->setPort("\\A", input_sig);
+ cell->setPort("\\Y", output_sig);
+ }
+ }
+ else if (c == 'n') {
+ // TODO: What is this?
+ uint32_t n = parse_xaiger_literal(f);
+ f.seekg(n);
+ }
+ }
+ else if (c == 'i' || c == 'l' || c == 'o') {
+ f.ignore(1);
+ if (!(f >> l1 >> s))
+ log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
+
+ if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
+ log_error("Line %u has invalid symbol position!\n", line_count);
+
+ RTLIL::Wire* wire;
+ if (c == 'i') wire = inputs[l1];
+ else if (c == 'l') wire = latches[l1];
+ else if (c == 'o') wire = outputs[l1];
+ else log_abort();
+
+ module->rename(wire, stringf("\\%s", s.c_str()));
+ std::getline(f, line); // Ignore up to start of next line
+ ++line_count;
+ }
+ else
+ log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
+ }
+
+ dict<RTLIL::IdString, int> wideports_cache;
+
+ if (!map_filename.empty()) {
+ std::ifstream mf(map_filename);
+ std::string type, symbol;
+ int variable, index;
+ while (mf >> type >> variable >> index >> symbol) {
+ RTLIL::IdString escaped_symbol = RTLIL::escape_id(symbol);
+ if (type == "input") {
+ log_assert(static_cast<unsigned>(variable) < inputs.size());
+ RTLIL::Wire* wire = inputs[variable];
+ log_assert(wire);
+ log_assert(wire->port_input);
+
+ if (index == 0)
+ module->rename(wire, RTLIL::escape_id(symbol));
+ else if (index > 0) {
+ module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", symbol.c_str(), index)));
+ if (wideports)
+ wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index);
+
+ }
+ }
+ else if (type == "output") {
+ log_assert(static_cast<unsigned>(variable) < outputs.size());
+ RTLIL::Wire* wire = outputs[variable];
+ log_assert(wire);
+ log_assert(wire->port_output);
+ if (index == 0)
+ module->rename(wire, RTLIL::escape_id(symbol));
+ else if (index > 0) {
+ module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", symbol.c_str(), index)));
+ if (wideports)
+ wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index);
+
+ }
+ }
+ else
+ log_error("Symbol type '%s' not recognised.\n", type.c_str());
+ }
+ }
+
+ for (auto &wp : wideports_cache)
+ {
+ auto name = wp.first;
+ int width = wp.second + 1;
+
+ RTLIL::Wire *wire = module->wire(name);
+ if (wire)
+ module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
+ wire = module->addWire(name, width);
+
+ for (int i = 0; i < width; i++) {
+ RTLIL::IdString other_name = name.str() + stringf("[%d]", i);
+ RTLIL::Wire *other_wire = module->wire(other_name);
+ if (other_wire) {
+ wire->port_input = other_wire->port_input;
+ wire->port_output = other_wire->port_output;
+ other_wire->port_input = false;
+ other_wire->port_output = false;
+ if (wire->port_output)
+ module->connect(other_wire, SigSpec(wire, i));
+ else
+ module->connect(SigSpec(wire, i), other_wire);
+ }
+ }
+ }
+
+ module->fixup_ports();
+ design->add(module);
+}
+
static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal)
{
const unsigned variable = literal >> 1;
@@ -138,7 +321,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
return wire;
}
-void AigerReader::parse_aiger_ascii()
+void AigerReader::parse_aiger_ascii(bool create_and)
{
std::string line;
std::stringstream ss;
@@ -229,11 +412,13 @@ void AigerReader::parse_aiger_ascii()
log_error("Line %u cannot be interpreted as an AND!\n", line_count);
log_debug("%d %d %d is an AND\n", l1, l2, l3);
- log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
- RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
- RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
- RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
- module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
+ if (create_and) {
+ log_assert(!(l1 & 1));
+ RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
+ RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
+ RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
+ module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
+ }
}
}
@@ -246,13 +431,14 @@ static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
return ref - (x | (ch << (7 * i)));
}
-void AigerReader::parse_aiger_binary()
+void AigerReader::parse_aiger_binary(bool create_and)
{
unsigned l1, l2, l3;
std::string line;
// Parse inputs
for (unsigned i = 1; i <= I; ++i) {
+ log_debug("%d is an input\n", i);
RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
wire->port_input = true;
inputs.push_back(wire);
@@ -332,18 +518,18 @@ void AigerReader::parse_aiger_binary()
l3 = parse_next_delta_literal(f, l2);
log_debug("%d %d %d is an AND\n", l1, l2, l3);
- log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
- RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
- RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
- RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
-
- RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
- and_cell->setPort("\\A", i1_wire);
- and_cell->setPort("\\B", i2_wire);
- and_cell->setPort("\\Y", o_wire);
+ if (create_and) {
+ log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
+ RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
+ RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
+ RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
+
+ RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
+ and_cell->setPort("\\A", i1_wire);
+ and_cell->setPort("\\B", i2_wire);
+ and_cell->setPort("\\Y", o_wire);
+ }
}
- std::getline(f, line); // Ignore up to start of next line
-
}
struct AigerFrontend : public Frontend {
@@ -369,6 +555,13 @@ struct AigerFrontend : public Frontend {
log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
log(" this name (default: clk)\n");
log("\n");
+ log(" -map <filename>\n");
+ log(" read file with port and latch symbols\n");
+ log("\n");
+ log(" -wideports\n");
+ log(" Merge ports that match the pattern 'name[int]' into a single\n");
+ log(" multi-bit port 'name'.\n");
+ log("\n");
}
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
@@ -376,6 +569,8 @@ struct AigerFrontend : public Frontend {
RTLIL::IdString clk_name = "\\clk";
RTLIL::IdString module_name;
+ std::string map_filename;
+ bool wideports = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
@@ -388,6 +583,14 @@ struct AigerFrontend : public Frontend {
clk_name = RTLIL::escape_id(args[++argidx]);
continue;
}
+ if (map_filename.empty() && arg == "-map" && argidx+1 < args.size()) {
+ map_filename = args[++argidx];
+ continue;
+ }
+ if (arg == "-wideports") {
+ wideports = true;
+ continue;
+ }
break;
}
extra_args(f, filename, args, argidx);
@@ -400,7 +603,7 @@ struct AigerFrontend : public Frontend {
#endif
}
- AigerReader reader(design, *f, module_name, clk_name);
+ AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports);
reader.parse_aiger();
}
} AigerFrontend;
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
index 39a77bd93..a1d2af9c9 100644
--- a/frontends/aiger/aigerparse.h
+++ b/frontends/aiger/aigerparse.h
@@ -30,6 +30,8 @@ struct AigerReader
std::istream &f;
RTLIL::IdString clk_name;
RTLIL::Module *module;
+ std::string map_filename;
+ bool wideports;
unsigned M, I, L, O, A;
unsigned B, C, J, F; // Optional in AIGER 1.9
@@ -39,10 +41,11 @@ struct AigerReader
std::vector<RTLIL::Wire*> latches;
std::vector<RTLIL::Wire*> outputs;
- AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name);
+ AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
void parse_aiger();
- void parse_aiger_ascii();
- void parse_aiger_binary();
+ void parse_xaiger();
+ void parse_aiger_ascii(bool create_and);
+ void parse_aiger_binary(bool create_and);
};
YOSYS_NAMESPACE_END
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 9531dd356..e66625228 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -942,16 +942,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node
case AST_CONSTANT:
+ case AST_REALVALUE:
{
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
-
is_signed = sign_hint;
- return RTLIL::SigSpec(bitsAsConst());
- }
- case AST_REALVALUE:
- {
+ if (type == AST_CONSTANT)
+ return RTLIL::SigSpec(bitsAsConst());
+
RTLIL::SigSpec sig = realAsConst(width_hint);
log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
return sig;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-17 04:16:29 +0000