diff options
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 2 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 5 | ||||
| -rw-r--r-- | frontends/ilang/ilang_lexer.l | 13 | ||||
| -rw-r--r-- | frontends/ilang/ilang_parser.y | 11 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 1 |
5 files changed, 23 insertions, 9 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index cbce0c990..92cf92fa8 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -30,7 +30,9 @@ #include <libkern/OSByteOrder.h> #define __builtin_bswap32 OSSwapInt32 #endif +#ifndef __STDC_FORMAT_MACROS #define __STDC_FORMAT_MACROS +#endif #include <inttypes.h> #include "kernel/yosys.h" diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index bdb48e82f..ced5e5cf9 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -420,9 +420,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, current_scope[node->str] = node; for (auto enode : node->children) { log_assert(enode->type==AST_ENUM_ITEM); - if (current_scope.count(enode->str) == 0) { + if (current_scope.count(enode->str) == 0) current_scope[enode->str] = enode; - } + else + log_file_error(filename, location.first_line, "enum item %s already exists\n", enode->str.c_str()); } } } diff --git a/frontends/ilang/ilang_lexer.l b/frontends/ilang/ilang_lexer.l index 4fd0ae855..62f53d18e 100644 --- a/frontends/ilang/ilang_lexer.l +++ b/frontends/ilang/ilang_lexer.l @@ -29,6 +29,7 @@ #pragma clang diagnostic ignored "-Wdeprecated-register" #endif +#include <cstdlib> #include "frontends/ilang/ilang_frontend.h" #include "ilang_parser.tab.hh" @@ -88,7 +89,16 @@ USING_YOSYS_NAMESPACE "."[0-9]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; } [0-9]+'[01xzm-]* { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_VALUE; } --?[0-9]+ { rtlil_frontend_ilang_yylval.integer = atoi(yytext); return TOK_INT; } +-?[0-9]+ { + char *end = nullptr; + long value = strtol(yytext, &end, 10); + if (end != yytext + strlen(yytext)) + return TOK_INVALID; // literal out of range of long + if (value < INT_MIN || value > INT_MAX) + return TOK_INVALID; // literal out of range of int (relevant mostly for LP64 platforms) + rtlil_frontend_ilang_yylval.integer = value; + return TOK_INT; +} \" { BEGIN(STRING); } <STRING>\\. { yymore(); } @@ -136,4 +146,3 @@ USING_YOSYS_NAMESPACE void *rtlil_frontend_ilang_avoid_input_warnings() { return (void*)&yyinput; } - diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y index 4e0b62edd..0522fa72a 100644 --- a/frontends/ilang/ilang_parser.y +++ b/frontends/ilang/ilang_parser.y @@ -169,7 +169,7 @@ wire_stmt: current_wire->attributes = attrbuf; attrbuf.clear(); } wire_options TOK_ID EOL { - if (current_module->wires_.count($4) != 0) + if (current_module->wire($4) != nullptr) rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of wire %s.", $4).c_str()); current_module->rename(current_wire, $4); free($4); @@ -179,6 +179,9 @@ wire_options: wire_options TOK_WIDTH TOK_INT { current_wire->width = $3; } | + wire_options TOK_WIDTH TOK_INVALID { + rtlil_frontend_ilang_yyerror("ilang error: invalid wire width"); + } | wire_options TOK_UPTO { current_wire->upto = true; } | @@ -229,7 +232,7 @@ memory_options: cell_stmt: TOK_CELL TOK_ID TOK_ID EOL { - if (current_module->cells_.count($3) != 0) + if (current_module->cell($3) != nullptr) rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell %s.", $3).c_str()); current_cell = current_module->addCell($3, $2); current_cell->attributes = attrbuf; @@ -424,9 +427,9 @@ sigspec: delete $1; } | TOK_ID { - if (current_module->wires_.count($1) == 0) + if (current_module->wire($1) == nullptr) rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str()); - $$ = new RTLIL::SigSpec(current_module->wires_[$1]); + $$ = new RTLIL::SigSpec(current_module->wire($1)); free($1); } | sigspec '[' TOK_INT ']' { diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index f850daacb..76373c2e4 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1736,7 +1736,6 @@ single_cell: ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2)); } '(' cell_port_list ')'{ SET_AST_NODE_LOC(astbuf2, @1, @$); - SET_AST_NODE_LOC(astbuf3, @1, @$); }; prim_list: |