RTLIL::State eval_ret = RTLIL::Sx;

if (cell->type == "$_NOT_") {

}

else if (cell->type == "$_AND_") {

goto eval_end;

}

RTLIL::SigBit sig_b = cell->getPort("\\B");

if (!eval(sig_b))

return false;

goto eval_end;

}

goto eval_end;

}

}

else log_abort();

RTLIL::Wire* n0 = module->wire("\\__0__");

if (n0)

// Parse footer (symbol table, comments, etc.)

unsigned l1;

RTLIL::Wire* n0 = module->wire("\\__0__");

if (n0)

// Parse footer (symbol table, comments, etc.)

std::string s;

log_error("Line %u cannot be interpreted as a latch!\n", line_count);

if (l3 == 0)

else if (l3 == 1)

else if (l3 == l1) {

//q_wire->attributes["\\init"] = RTLIL::Sx;

}

}

else {

// AIGER latches are assumed to be initialized to zero

}

latches.push_back(q_wire);

}

log_error("Line %u cannot be interpreted as a latch!\n", line_count);

if (l3 == 0)

else if (l3 == 1)

else if (l3 == l1) {

//q_wire->attributes["\\init"] = RTLIL::Sx;

}

}

else {

// AIGER latches are assumed to be initialized to zero

}

latches.push_back(q_wire);

}

if (!bits.empty()) {

fprintf(f, " bits='");

for (size_t i = bits.size(); i > 0; i--)

bits[i-1] == RTLIL::Sx ? 'x' :

bits[i-1] == RTLIL::Sz ? 'z' : '?');

fprintf(f, "'(%d)", GetSize(bits));

node->integer = v;

node->is_signed = is_signed;

for (int i = 0; i < width; i++) {

v = v >> 1;

}

node->range_valid = true;

node->bits = v;

for (size_t i = 0; i < 32; i++) {

if (i < node->bits.size())

else if (is_signed && !node->bits.empty())

}

node->range_valid = true;

node->range_left = node->bits.size()-1;

for (size_t i = 0; i < str.size(); i++) {

unsigned char ch = str[str.size() - i - 1];

for (int j = 0; j < 8; j++) {

ch = ch >> 1;

}

}

bool AstNode::bits_only_01() const

{

for (auto bit : bits)

return false;

return true;

}

}

}

(*it)->str = (*it)->str.substr(1);

if (defer)

{

std::string stripped_name = name.str();

stripped_name = stripped_name.substr(9);

log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());

AstNode *child = *it;

if (child->type == AST_CELLTYPE) {

cell->type = child->str;

cell->type = cell->type.substr(1);

continue;

}

if (attr.first.str().rfind("\\via_celltype_defparam_", 0) == 0)

{

AstNode *cell_arg = new AstNode(AST_PARASET, attr.second->clone());

cell->children.push_back(cell_arg);

}

std::getline(f, line);

for (int i = 0; i < GetSize(line); i++) {

line[i] = ' ';

line[i+1] = ' ';

in_comment = false;

continue;

}

in_comment = true;

if (in_comment)

line[i] = ' ';

while (1)

{

token = next_token(line, " \t\r\n");

break;

if (token[0] == '@') {

veri_file::DefineMacro("VERIFIC");

veri_file::DefineMacro(args[argidx] == "-formal" ? "FORMAL" : "SYNTHESIS");

std::string name = args[argidx].substr(2);

if (args[argidx] == "-D") {

if (++argidx >= GetSize(args))

break;

}

cmd_error(args, argidx, "unknown option");

if (mode_all)

for (int i = 0; i < GetSize(nodes); i++)

{

if (next_state_sig[i] != State::S0) {

} else {

module->connect(state_wire[i], State::S0);

}

if (base == 10) {

while (!digits.empty())

} else {

int bits_per_digit = my_ilog2(base-1);

for (auto it = digits.rbegin(), e = digits.rend(); it != e; it++) {

else if (*it == 0xf2)

data.push_back(RTLIL::Sa);

else

}

}

}

int len = GetSize(data);

if (len_in_bits < 0) {

if (len < 32)

return;

}

log_file_error(current_filename, get_line_num(), "Unsized constant must have width of 1 bit, but have %d bits!\n", len);

for (len = len - 1; len >= 0; len--)

break;

len += 1;

} else {

len += 2;

data.resize(len_in_bits, msb);

for (int i = 0; i < len; i++) {

unsigned char ch = str[len - i];

for (int j = 0; j < 8; j++) {

ch = ch >> 1;

}

}

if (*endptr == 0) {

std::vector<RTLIL::State> data;

my_strtobin(data, str, -1, 10, case_type, false);

return AstNode::mkconst_bits(data, true);

}

}

}

if (len_in_bits < 0) {

}

return AstNode::mkconst_bits(data, is_signed, is_unsized);

}

$$ = $1;

} |

hierarchical_id TOK_PACKAGESEP TOK_ID {

*$1 += "::" + $3->substr(1);

else

*$1 += "::" + *$3;

$$ = $1;

} |

hierarchical_id '.' TOK_ID {

*$1 += "." + $3->substr(1);

else

*$1 += "." + *$3;

$$ = $1;

} |

'(' expr ')' TOK_CONSTVAL {

frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());

AstNode *bits = $2;

AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);

delete $4;

} |

hierarchical_id TOK_CONSTVAL {

frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());

AstNode *bits = new AstNode(AST_IDENTIFIER);

bits->str = *$1;