diff options
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 08c79beae..97a2946a6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/macc.h" #include "frontends/verilog/verilog_frontend.h" #include "backends/ilang/ilang_backend.h" @@ -633,6 +634,17 @@ namespace { return; } + if (cell->type == "$macc") { + param("\\CONFIG"); + param("\\CONFIG_WIDTH"); + port("\\A", param("\\A_WIDTH")); + port("\\B", param("\\B_WIDTH")); + port("\\Y", param("\\Y_WIDTH")); + check_expected(); + Macc().from_cell(cell); + return; + } + if (cell->type == "$logic_not") { param_bool("\\A_SIGNED"); port("\\A", param("\\A_WIDTH")); @@ -1781,7 +1793,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) return; } - bool signedness_ab = !type.in("$slice", "$concat"); + bool signedness_ab = !type.in("$slice", "$concat", "$macc"); if (connections_.count("\\A")) { if (signedness_ab) { |