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-rw-r--r--kernel/rtlil.cc171
1 files changed, 88 insertions, 83 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 1a6e386ff..4d0aadbb5 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -348,9 +348,9 @@ namespace {
void port(const char *name, int width)
{
- if (cell->connections.count(name) == 0)
+ if (cell->connections_.count(name) == 0)
error(__LINE__);
- if (cell->connections.at(name).size() != width)
+ if (cell->connections_.at(name).size() != width)
error(__LINE__);
expected_ports.insert(name);
}
@@ -360,7 +360,7 @@ namespace {
for (auto &para : cell->parameters)
if (expected_params.count(para.first) == 0)
error(__LINE__);
- for (auto &conn : cell->connections)
+ for (auto &conn : cell->connections_)
if (expected_ports.count(conn.first) == 0)
error(__LINE__);
@@ -379,13 +379,13 @@ namespace {
for (const char *p = ports; *p; p++) {
char portname[3] = { '\\', *p, 0 };
- if (cell->connections.count(portname) == 0)
+ if (cell->connections_.count(portname) == 0)
error(__LINE__);
- if (cell->connections.at(portname).size() != 1)
+ if (cell->connections_.at(portname).size() != 1)
error(__LINE__);
}
- for (auto &conn : cell->connections) {
+ for (auto &conn : cell->connections_) {
if (conn.first.size() != 2 || conn.first.at(0) != '\\')
error(__LINE__);
if (strchr(ports, conn.first.at(1)) == NULL)
@@ -734,7 +734,7 @@ void RTLIL::Module::check()
assert(it.first == it.second->name);
assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
- for (auto &it2 : it.second->connections) {
+ for (auto &it2 : it.second->connections_) {
assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
it2.second.check();
}
@@ -754,7 +754,7 @@ void RTLIL::Module::check()
// FIXME: More checks here..
}
- for (auto &it : connections) {
+ for (auto &it : connections_) {
assert(it.first.size() == it.second.size());
it.first.check();
it.second.check();
@@ -773,7 +773,7 @@ void RTLIL::Module::optimize()
void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
{
new_mod->name = name;
- new_mod->connections = connections;
+ new_mod->connections_ = connections_;
new_mod->attributes = attributes;
for (auto &it : wires)
@@ -873,6 +873,11 @@ static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
return a->port_id < b->port_id;
}
+void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
+{
+ connections_.push_back(RTLIL::SigSig(lhs, rhs));
+}
+
void RTLIL::Module::fixup_ports()
{
std::vector<RTLIL::Wire*> all_ports;
@@ -909,7 +914,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
{
RTLIL::Cell *cell = addCell(name, other->type);
- cell->connections = other->connections;
+ cell->connections_ = other->connections_;
cell->parameters = other->parameters;
cell->attributes = other->attributes;
return cell;
@@ -923,8 +928,8 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
cell->parameters["\\A_SIGNED"] = is_signed; \
cell->parameters["\\A_WIDTH"] = sig_a.size(); \
cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
- cell->connections["\\A"] = sig_a; \
- cell->connections["\\Y"] = sig_y; \
+ cell->connections_["\\A"] = sig_a; \
+ cell->connections_["\\Y"] = sig_y; \
add(cell); \
return cell; \
} \
@@ -955,9 +960,9 @@ DEF_METHOD(LogicNot, 1, "$logic_not")
cell->parameters["\\A_WIDTH"] = sig_a.size(); \
cell->parameters["\\B_WIDTH"] = sig_b.size(); \
cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
- cell->connections["\\A"] = sig_a; \
- cell->connections["\\B"] = sig_b; \
- cell->connections["\\Y"] = sig_y; \
+ cell->connections_["\\A"] = sig_a; \
+ cell->connections_["\\B"] = sig_b; \
+ cell->connections_["\\Y"] = sig_y; \
add(cell); \
return cell; \
} \
@@ -999,10 +1004,10 @@ DEF_METHOD(LogicOr, 1, "$logic_or")
cell->parameters["\\WIDTH"] = sig_a.size(); \
cell->parameters["\\WIDTH"] = sig_b.size(); \
if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
- cell->connections["\\A"] = sig_a; \
- cell->connections["\\B"] = sig_b; \
- cell->connections["\\S"] = sig_s; \
- cell->connections["\\Y"] = sig_y; \
+ cell->connections_["\\A"] = sig_a; \
+ cell->connections_["\\B"] = sig_b; \
+ cell->connections_["\\S"] = sig_s; \
+ cell->connections_["\\Y"] = sig_y; \
add(cell); \
return cell; \
} \
@@ -1021,8 +1026,8 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1)
RTLIL::Cell *cell = new RTLIL::Cell; \
cell->name = name; \
cell->type = _type; \
- cell->connections["\\" #_P1] = sig1; \
- cell->connections["\\" #_P2] = sig2; \
+ cell->connections_["\\" #_P1] = sig1; \
+ cell->connections_["\\" #_P2] = sig2; \
add(cell); \
return cell; \
} \
@@ -1036,9 +1041,9 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1)
RTLIL::Cell *cell = new RTLIL::Cell; \
cell->name = name; \
cell->type = _type; \
- cell->connections["\\" #_P1] = sig1; \
- cell->connections["\\" #_P2] = sig2; \
- cell->connections["\\" #_P3] = sig3; \
+ cell->connections_["\\" #_P1] = sig1; \
+ cell->connections_["\\" #_P2] = sig2; \
+ cell->connections_["\\" #_P3] = sig3; \
add(cell); \
return cell; \
} \
@@ -1052,10 +1057,10 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1)
RTLIL::Cell *cell = new RTLIL::Cell; \
cell->name = name; \
cell->type = _type; \
- cell->connections["\\" #_P1] = sig1; \
- cell->connections["\\" #_P2] = sig2; \
- cell->connections["\\" #_P3] = sig3; \
- cell->connections["\\" #_P4] = sig4; \
+ cell->connections_["\\" #_P1] = sig1; \
+ cell->connections_["\\" #_P2] = sig2; \
+ cell->connections_["\\" #_P3] = sig3; \
+ cell->connections_["\\" #_P4] = sig4; \
add(cell); \
return cell; \
} \
@@ -1083,9 +1088,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\B_WIDTH"] = sig_b.size();
cell->parameters["\\Y_WIDTH"] = sig_y.size();
- cell->connections["\\A"] = sig_a;
- cell->connections["\\B"] = sig_b;
- cell->connections["\\Y"] = sig_y;
+ cell->connections_["\\A"] = sig_a;
+ cell->connections_["\\B"] = sig_b;
+ cell->connections_["\\Y"] = sig_y;
add(cell);
return cell;
}
@@ -1098,8 +1103,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a,
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\Y_WIDTH"] = sig_y.size();
cell->parameters["\\OFFSET"] = offset;
- cell->connections["\\A"] = sig_a;
- cell->connections["\\Y"] = sig_y;
+ cell->connections_["\\A"] = sig_a;
+ cell->connections_["\\Y"] = sig_y;
add(cell);
return cell;
}
@@ -1111,9 +1116,9 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a
cell->type = "$concat";
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\B_WIDTH"] = sig_b.size();
- cell->connections["\\A"] = sig_a;
- cell->connections["\\B"] = sig_b;
- cell->connections["\\Y"] = sig_y;
+ cell->connections_["\\A"] = sig_a;
+ cell->connections_["\\B"] = sig_b;
+ cell->connections_["\\Y"] = sig_y;
add(cell);
return cell;
}
@@ -1125,8 +1130,8 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R
cell->type = "$lut";
cell->parameters["\\LUT"] = lut;
cell->parameters["\\WIDTH"] = sig_i.size();
- cell->connections["\\I"] = sig_i;
- cell->connections["\\O"] = sig_o;
+ cell->connections_["\\I"] = sig_i;
+ cell->connections_["\\O"] = sig_o;
add(cell);
return cell;
}
@@ -1136,8 +1141,8 @@ RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = name;
cell->type = "$assert";
- cell->connections["\\A"] = sig_a;
- cell->connections["\\EN"] = sig_en;
+ cell->connections_["\\A"] = sig_a;
+ cell->connections_["\\EN"] = sig_en;
add(cell);
return cell;
}
@@ -1150,9 +1155,9 @@ RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set,
cell->parameters["\\SET_POLARITY"] = set_polarity;
cell->parameters["\\CLR_POLARITY"] = clr_polarity;
cell->parameters["\\WIDTH"] = sig_q.size();
- cell->connections["\\SET"] = sig_set;
- cell->connections["\\CLR"] = sig_clr;
- cell->connections["\\Q"] = sig_q;
+ cell->connections_["\\SET"] = sig_set;
+ cell->connections_["\\CLR"] = sig_clr;
+ cell->connections_["\\Q"] = sig_q;
add(cell);
return cell;
}
@@ -1164,9 +1169,9 @@ RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk,
cell->type = "$dff";
cell->parameters["\\CLK_POLARITY"] = clk_polarity;
cell->parameters["\\WIDTH"] = sig_q.size();
- cell->connections["\\CLK"] = sig_clk;
- cell->connections["\\D"] = sig_d;
- cell->connections["\\Q"] = sig_q;
+ cell->connections_["\\CLK"] = sig_clk;
+ cell->connections_["\\D"] = sig_d;
+ cell->connections_["\\Q"] = sig_q;
add(cell);
return cell;
}
@@ -1181,11 +1186,11 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_cl
cell->parameters["\\SET_POLARITY"] = set_polarity;
cell->parameters["\\CLR_POLARITY"] = clr_polarity;
cell->parameters["\\WIDTH"] = sig_q.size();
- cell->connections["\\CLK"] = sig_clk;
- cell->connections["\\SET"] = sig_set;
- cell->connections["\\CLR"] = sig_clr;
- cell->connections["\\D"] = sig_d;
- cell->connections["\\Q"] = sig_q;
+ cell->connections_["\\CLK"] = sig_clk;
+ cell->connections_["\\SET"] = sig_set;
+ cell->connections_["\\CLR"] = sig_clr;
+ cell->connections_["\\D"] = sig_d;
+ cell->connections_["\\Q"] = sig_q;
add(cell);
return cell;
}
@@ -1200,10 +1205,10 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk
cell->parameters["\\ARST_POLARITY"] = arst_polarity;
cell->parameters["\\ARST_VALUE"] = arst_value;
cell->parameters["\\WIDTH"] = sig_q.size();
- cell->connections["\\CLK"] = sig_clk;
- cell->connections["\\ARST"] = sig_arst;
- cell->connections["\\D"] = sig_d;
- cell->connections["\\Q"] = sig_q;
+ cell->connections_["\\CLK"] = sig_clk;
+ cell->connections_["\\ARST"] = sig_arst;
+ cell->connections_["\\D"] = sig_d;
+ cell->connections_["\\Q"] = sig_q;
add(cell);
return cell;
}
@@ -1215,9 +1220,9 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e
cell->type = "$dlatch";
cell->parameters["\\EN_POLARITY"] = en_polarity;
cell->parameters["\\WIDTH"] = sig_q.size();
- cell->connections["\\EN"] = sig_en;
- cell->connections["\\D"] = sig_d;
- cell->connections["\\Q"] = sig_q;
+ cell->connections_["\\EN"] = sig_en;
+ cell->connections_["\\D"] = sig_d;
+ cell->connections_["\\Q"] = sig_q;
add(cell);
return cell;
}
@@ -1232,11 +1237,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig
cell->parameters["\\SET_POLARITY"] = set_polarity;
cell->parameters["\\CLR_POLARITY"] = clr_polarity;
cell->parameters["\\WIDTH"] = sig_q.size();
- cell->connections["\\EN"] = sig_en;
- cell->connections["\\SET"] = sig_set;
- cell->connections["\\CLR"] = sig_clr;
- cell->connections["\\D"] = sig_d;
- cell->connections["\\Q"] = sig_q;
+ cell->connections_["\\EN"] = sig_en;
+ cell->connections_["\\SET"] = sig_set;
+ cell->connections_["\\CLR"] = sig_clr;
+ cell->connections_["\\D"] = sig_d;
+ cell->connections_["\\Q"] = sig_q;
add(cell);
return cell;
}
@@ -1246,9 +1251,9 @@ RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = name;
cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
- cell->connections["\\C"] = sig_clk;
- cell->connections["\\D"] = sig_d;
- cell->connections["\\Q"] = sig_q;
+ cell->connections_["\\C"] = sig_clk;
+ cell->connections_["\\D"] = sig_d;
+ cell->connections_["\\Q"] = sig_q;
add(cell);
return cell;
}
@@ -1259,11 +1264,11 @@ RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec si
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = name;
cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
- cell->connections["\\C"] = sig_clk;
- cell->connections["\\S"] = sig_set;
- cell->connections["\\R"] = sig_clr;
- cell->connections["\\D"] = sig_d;
- cell->connections["\\Q"] = sig_q;
+ cell->connections_["\\C"] = sig_clk;
+ cell->connections_["\\S"] = sig_set;
+ cell->connections_["\\R"] = sig_clr;
+ cell->connections_["\\D"] = sig_d;
+ cell->connections_["\\Q"] = sig_q;
add(cell);
return cell;
}
@@ -1274,10 +1279,10 @@ RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = name;
cell->type = stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0');
- cell->connections["\\C"] = sig_clk;
- cell->connections["\\R"] = sig_arst;
- cell->connections["\\D"] = sig_d;
- cell->connections["\\Q"] = sig_q;
+ cell->connections_["\\C"] = sig_clk;
+ cell->connections_["\\R"] = sig_arst;
+ cell->connections_["\\D"] = sig_d;
+ cell->connections_["\\Q"] = sig_q;
add(cell);
return cell;
}
@@ -1287,9 +1292,9 @@ RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec s
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = name;
cell->type = stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N');
- cell->connections["\\E"] = sig_en;
- cell->connections["\\D"] = sig_d;
- cell->connections["\\Q"] = sig_q;
+ cell->connections_["\\E"] = sig_en;
+ cell->connections_["\\D"] = sig_d;
+ cell->connections_["\\Q"] = sig_q;
add(cell);
return cell;
}
@@ -1300,11 +1305,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = name;
cell->type = stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
- cell->connections["\\E"] = sig_en;
- cell->connections["\\S"] = sig_set;
- cell->connections["\\R"] = sig_clr;
- cell->connections["\\D"] = sig_d;
- cell->connections["\\Q"] = sig_q;
+ cell->connections_["\\E"] = sig_en;
+ cell->connections_["\\S"] = sig_set;
+ cell->connections_["\\R"] = sig_clr;
+ cell->connections_["\\D"] = sig_d;
+ cell->connections_["\\Q"] = sig_q;
add(cell);
return cell;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 16:22:15 +0000