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-rw-r--r--kernel/log.cc4
-rw-r--r--kernel/log.h1
-rw-r--r--kernel/register.cc8
-rw-r--r--kernel/register.h4
-rw-r--r--kernel/rtlil.cc8
-rw-r--r--kernel/rtlil.h3
-rw-r--r--kernel/yosys.h1
7 files changed, 23 insertions, 6 deletions
diff --git a/kernel/log.cc b/kernel/log.cc
index e0a60ca12..c5ba0d10d 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -551,6 +551,10 @@ void log_dump_val_worker(RTLIL::SigSpec v) {
log("%s", log_signal(v));
}
+void log_dump_val_worker(RTLIL::State v) {
+ log("%s", log_signal(v));
+}
+
const char *log_signal(const RTLIL::SigSpec &sig, bool autoint)
{
std::stringstream buf;
diff --git a/kernel/log.h b/kernel/log.h
index 5f53f533a..1f15f3459 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -292,6 +292,7 @@ static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p
static inline void log_dump_args_worker(const char *p YS_ATTRIBUTE(unused)) { log_assert(*p == 0); }
void log_dump_val_worker(RTLIL::IdString v);
void log_dump_val_worker(RTLIL::SigSpec v);
+void log_dump_val_worker(RTLIL::State v);
template<typename K, typename T, typename OPS>
static inline void log_dump_val_worker(dict<K, T, OPS> &v) {
diff --git a/kernel/register.cc b/kernel/register.cc
index 8131fa279..37f2e5e1b 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -439,7 +439,7 @@ void Frontend::execute(std::vector<std::string> args, RTLIL::Design *design)
FILE *Frontend::current_script_file = NULL;
std::string Frontend::last_here_document;
-void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx)
+void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_input)
{
bool called_with_fp = f != NULL;
@@ -489,7 +489,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
next_args.insert(next_args.end(), filenames.begin()+1, filenames.end());
}
std::ifstream *ff = new std::ifstream;
- ff->open(filename.c_str());
+ ff->open(filename.c_str(), bin_input ? std::ifstream::binary : std::ifstream::in);
yosys_input_files.insert(filename);
if (ff->fail())
delete ff;
@@ -612,7 +612,7 @@ void Backend::execute(std::vector<std::string> args, RTLIL::Design *design)
delete f;
}
-void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx)
+void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output)
{
bool called_with_fp = f != NULL;
@@ -647,7 +647,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<st
#endif
} else {
std::ofstream *ff = new std::ofstream;
- ff->open(filename.c_str(), std::ofstream::trunc);
+ ff->open(filename.c_str(), bin_output ? (std::ofstream::trunc | std::ofstream::binary) : std::ofstream::trunc);
yosys_output_files.insert(filename);
if (ff->fail()) {
delete ff;
diff --git a/kernel/register.h b/kernel/register.h
index c74029823..85d552f0d 100644
--- a/kernel/register.h
+++ b/kernel/register.h
@@ -94,7 +94,7 @@ struct Frontend : Pass
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;
static std::vector<std::string> next_args;
- void extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx);
+ void extra_args(std::istream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_input = false);
static void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::string command);
static void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::vector<std::string> args);
@@ -109,7 +109,7 @@ struct Backend : Pass
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL;
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;
- void extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx);
+ void extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);
static void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command);
static void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector<std::string> args);
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index f42f5430f..bd2fd91a3 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3083,6 +3083,7 @@ void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RT
log_assert(other != NULL);
log_assert(width_ == other->width_);
+ if (rules.empty()) return;
unpack();
other->unpack();
@@ -3107,6 +3108,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules
log_assert(other != NULL);
log_assert(width_ == other->width_);
+ if (rules.empty()) return;
unpack();
other->unpack();
@@ -3552,6 +3554,12 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
if (width_ != other.width_)
return false;
+ // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
+ // since the RHS will contain one SigChunk of width 0 causing
+ // the size check below to fail
+ if (width_ == 0)
+ return true;
+
pack();
other.pack();
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index c08653b65..e5b24cc02 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -609,8 +609,11 @@ struct RTLIL::Const
std::string decode_string() const;
inline int size() const { return bits.size(); }
+ inline bool empty() const { return bits.empty(); }
inline RTLIL::State &operator[](int index) { return bits.at(index); }
inline const RTLIL::State &operator[](int index) const { return bits.at(index); }
+ inline decltype(bits)::iterator begin() { return bits.begin(); }
+ inline decltype(bits)::iterator end() { return bits.end(); }
bool is_fully_zero() const;
bool is_fully_ones() const;
diff --git a/kernel/yosys.h b/kernel/yosys.h
index a80cb00b4..179bfe07a 100644
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -210,6 +210,7 @@ namespace RTLIL {
struct Module;
struct Design;
struct Monitor;
+ enum State : unsigned char;
}
namespace AST {