4 files changed, 26 insertions, 11 deletions
diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h
index 4f4bc37a0..05b2bbc24 100644
--- a/kernel/bitpattern.h
+++ b/kernel/bitpattern.h
@@ -35,10 +35,8 @@ struct BitPatternPool
 		if (width > 0) {
 			std::vector<RTLIL::State> pattern(width);
 			for (int i = 0; i < width; i++) {
-				RTLIL::SigSpec s = sig.extract(i, 1);
-				assert(s.chunks().size() == 1);
-				if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1)
-					pattern[i] = s.chunks()[0].data.bits[0];
+				if (sig[i].wire == NULL && sig[i].data <= RTLIL::State::S1)
+					pattern[i] = sig[i].data;
 				else
 					pattern[i] = RTLIL::State::Sa;
 			}
@@ -59,9 +57,7 @@ struct BitPatternPool
 
 	bits_t sig2bits(RTLIL::SigSpec sig)
 	{
-		assert(sig.is_fully_const());
-		assert(sig.chunks().size() == 1);
-		bits_t bits = sig.chunks()[0].data.bits;
+		bits_t bits = sig.as_const().bits;
 		for (auto &b : bits)
 			if (b > RTLIL::State::S1)
 				b = RTLIL::State::Sa;
diff --git a/kernel/consteval.h b/kernel/consteval.h
index 3a8ef44a0..7b1b798c8 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -207,9 +207,9 @@ struct ConstEval
 		if (sig.is_fully_const())
 			return true;
 
-		for (size_t i = 0; i < sig.chunks().size(); i++)
-			if (sig.chunks()[i].wire != NULL)
-				undef.append(sig.chunks()[i]);
+		for (auto &c : sig.chunks())
+			if (c.wire != NULL)
+				undef.append(c);
 		return false;
 	}
 
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 8e509f360..f741e2a34 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1999,6 +1999,14 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
 	return true;
 }
 
+bool RTLIL::SigSpec::is_wire() const
+{
+	cover("kernel.rtlil.sigspec.is_wire");
+
+	pack();
+	return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
+}
+
 bool RTLIL::SigSpec::is_fully_const() const
 {
 	cover("kernel.rtlil.sigspec.is_fully_const");
@@ -2104,6 +2112,15 @@ RTLIL::Const RTLIL::SigSpec::as_const() const
 	return RTLIL::Const();
 }
 
+RTLIL::Wire *RTLIL::SigSpec::as_wire() const
+{
+	cover("kernel.rtlil.sigspec.as_wire");
+
+	pack();
+	assert(is_wire());
+	return chunks_[0].wire;
+}
+
 bool RTLIL::SigSpec::match(std::string pattern) const
 {
 	cover("kernel.rtlil.sigspec.match");
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 68eee46ea..a4b7e8492 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -576,6 +576,7 @@ public:
 	bool operator ==(const RTLIL::SigSpec &other) const;
 	inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }
 
+	bool is_wire() const;
 	bool is_fully_const() const;
 	bool is_fully_def() const;
 	bool is_fully_undef() const;
@@ -585,6 +586,7 @@ public:
 	int as_int() const;
 	std::string as_string() const;
 	RTLIL::Const as_const() const;
+	RTLIL::Wire *as_wire() const;
 
 	bool match(std::string pattern) const;
 
@@ -612,7 +614,7 @@ inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {
 
 inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
 	assert(sig.size() == 1 && sig.chunks().size() == 1);
-	*this = SigBit(sig.chunks()[0]);
+	*this = SigBit(sig.chunks().front());
 }
 
 struct RTLIL::CaseRule {