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-rw-r--r--kernel/celltypes.h31
-rw-r--r--kernel/consteval.h22
-rw-r--r--kernel/cost.h148
-rw-r--r--kernel/driver.cc6
-rw-r--r--kernel/macc.h42
-rw-r--r--kernel/register.cc24
-rw-r--r--kernel/rtlil.cc22
-rw-r--r--kernel/rtlil.h14
-rw-r--r--kernel/satgen.h2
-rw-r--r--kernel/yosys.cc60
10 files changed, 200 insertions, 171 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index d2594bc46..1256fbcba 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -139,13 +139,10 @@ struct CellTypes
setup_type("$fa", {A, B, C}, {X, Y}, true);
}
- void setup_internals_mem()
+ void setup_internals_ff()
{
IdString SET = "\\SET", CLR = "\\CLR", CLK = "\\CLK", ARST = "\\ARST", EN = "\\EN";
- IdString Q = "\\Q", D = "\\D", ADDR = "\\ADDR", DATA = "\\DATA", RD_EN = "\\RD_EN";
- IdString RD_CLK = "\\RD_CLK", RD_ADDR = "\\RD_ADDR", WR_CLK = "\\WR_CLK", WR_EN = "\\WR_EN";
- IdString WR_ADDR = "\\WR_ADDR", WR_DATA = "\\WR_DATA", RD_DATA = "\\RD_DATA";
- IdString CTRL_IN = "\\CTRL_IN", CTRL_OUT = "\\CTRL_OUT";
+ IdString Q = "\\Q", D = "\\D";
setup_type("$sr", {SET, CLR}, {Q});
setup_type("$ff", {D}, {Q});
@@ -156,6 +153,18 @@ struct CellTypes
setup_type("$dlatch", {EN, D}, {Q});
setup_type("$dlatchsr", {EN, SET, CLR, D}, {Q});
+ }
+
+ void setup_internals_mem()
+ {
+ setup_internals_ff();
+
+ IdString CLK = "\\CLK", ARST = "\\ARST", EN = "\\EN";
+ IdString ADDR = "\\ADDR", DATA = "\\DATA", RD_EN = "\\RD_EN";
+ IdString RD_CLK = "\\RD_CLK", RD_ADDR = "\\RD_ADDR", WR_CLK = "\\WR_CLK", WR_EN = "\\WR_EN";
+ IdString WR_ADDR = "\\WR_ADDR", WR_DATA = "\\WR_DATA", RD_DATA = "\\RD_DATA";
+ IdString CTRL_IN = "\\CTRL_IN", CTRL_OUT = "\\CTRL_OUT";
+
setup_type("$memrd", {CLK, EN, ADDR}, {DATA});
setup_type("$memwr", {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>());
setup_type("$meminit", {ADDR, DATA}, pool<RTLIL::IdString>());
@@ -273,8 +282,8 @@ struct CellTypes
static RTLIL::Const eval_not(RTLIL::Const v)
{
for (auto &bit : v.bits)
- if (bit == RTLIL::S0) bit = RTLIL::S1;
- else if (bit == RTLIL::S1) bit = RTLIL::S0;
+ if (bit == State::S0) bit = State::S1;
+ else if (bit == State::S1) bit = State::S0;
return v;
}
@@ -380,15 +389,15 @@ struct CellTypes
std::vector<RTLIL::State> t = cell->parameters.at("\\LUT").bits;
while (GetSize(t) < (1 << width))
- t.push_back(RTLIL::S0);
+ t.push_back(State::S0);
t.resize(1 << width);
for (int i = width-1; i >= 0; i--) {
RTLIL::State sel = arg1.bits.at(i);
std::vector<RTLIL::State> new_t;
- if (sel == RTLIL::S0)
+ if (sel == State::S0)
new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2);
- else if (sel == RTLIL::S1)
+ else if (sel == State::S1)
new_t = std::vector<RTLIL::State>(t.begin() + GetSize(t)/2, t.end());
else
for (int j = 0; j < GetSize(t)/2; j++)
@@ -407,7 +416,7 @@ struct CellTypes
std::vector<RTLIL::State> t = cell->parameters.at("\\TABLE").bits;
while (GetSize(t) < width*depth*2)
- t.push_back(RTLIL::S0);
+ t.push_back(State::S0);
RTLIL::State default_ret = State::S0;
diff --git a/kernel/consteval.h b/kernel/consteval.h
index f70dfa0fb..521ce96d4 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -114,8 +114,8 @@ struct ConstEval
bool carry = sig_ci.as_bool();
for (int i = 0; i < GetSize(coval); i++) {
- carry = (sig_g[i] == RTLIL::S1) || (sig_p[i] == RTLIL::S1 && carry);
- coval.bits[i] = carry ? RTLIL::S1 : RTLIL::S0;
+ carry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);
+ coval.bits[i] = carry ? State::S1 : State::S0;
}
set(sig_co, coval);
@@ -254,8 +254,8 @@ struct ConstEval
sig_a.extend_u0(GetSize(sig_y), signed_a);
sig_b.extend_u0(GetSize(sig_y), signed_b);
- bool carry = sig_ci[0] == RTLIL::S1;
- bool b_inv = sig_bi[0] == RTLIL::S1;
+ bool carry = sig_ci[0] == State::S1;
+ bool b_inv = sig_bi[0] == State::S1;
for (int i = 0; i < GetSize(sig_y); i++)
{
@@ -264,22 +264,22 @@ struct ConstEval
if (!x_inputs.is_fully_def()) {
set(sig_x[i], RTLIL::Sx);
} else {
- bool bit_a = sig_a[i] == RTLIL::S1;
- bool bit_b = (sig_b[i] == RTLIL::S1) != b_inv;
+ bool bit_a = sig_a[i] == State::S1;
+ bool bit_b = (sig_b[i] == State::S1) != b_inv;
bool bit_x = bit_a != bit_b;
- set(sig_x[i], bit_x ? RTLIL::S1 : RTLIL::S0);
+ set(sig_x[i], bit_x ? State::S1 : State::S0);
}
if (any_input_undef) {
set(sig_y[i], RTLIL::Sx);
set(sig_co[i], RTLIL::Sx);
} else {
- bool bit_a = sig_a[i] == RTLIL::S1;
- bool bit_b = (sig_b[i] == RTLIL::S1) != b_inv;
+ bool bit_a = sig_a[i] == State::S1;
+ bool bit_b = (sig_b[i] == State::S1) != b_inv;
bool bit_y = (bit_a != bit_b) != carry;
carry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry);
- set(sig_y[i], bit_y ? RTLIL::S1 : RTLIL::S0);
- set(sig_co[i], carry ? RTLIL::S1 : RTLIL::S0);
+ set(sig_y[i], bit_y ? State::S1 : State::S0);
+ set(sig_co[i], carry ? State::S1 : State::S0);
}
}
}
diff --git a/kernel/cost.h b/kernel/cost.h
index e8e077ff5..10fa50fb3 100644
--- a/kernel/cost.h
+++ b/kernel/cost.h
@@ -24,86 +24,92 @@
YOSYS_NAMESPACE_BEGIN
-int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr, bool cmos_cost = false);
-
-inline int get_cell_cost(RTLIL::IdString type, const dict<RTLIL::IdString, RTLIL::Const> &parameters = dict<RTLIL::IdString, RTLIL::Const>(),
- RTLIL::Design *design = nullptr, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr, bool cmos_cost = false)
+struct CellCosts
{
- static dict<RTLIL::IdString, int> gate_cost = {
- { "$_BUF_", 1 },
- { "$_NOT_", 2 },
- { "$_AND_", 4 },
- { "$_NAND_", 4 },
- { "$_OR_", 4 },
- { "$_NOR_", 4 },
- { "$_ANDNOT_", 4 },
- { "$_ORNOT_", 4 },
- { "$_XOR_", 8 },
- { "$_XNOR_", 8 },
- { "$_AOI3_", 6 },
- { "$_OAI3_", 6 },
- { "$_AOI4_", 8 },
- { "$_OAI4_", 8 },
- { "$_MUX_", 4 },
- { "$_NMUX_", 4 }
- };
-
- // match costs in "stat -tech cmos"
- static dict<RTLIL::IdString, int> cmos_gate_cost = {
- { "$_BUF_", 1 },
- { "$_NOT_", 2 },
- { "$_AND_", 6 },
- { "$_NAND_", 4 },
- { "$_OR_", 6 },
- { "$_NOR_", 4 },
- { "$_ANDNOT_", 6 },
- { "$_ORNOT_", 6 },
- { "$_XOR_", 12 },
- { "$_XNOR_", 12 },
- { "$_AOI3_", 6 },
- { "$_OAI3_", 6 },
- { "$_AOI4_", 8 },
- { "$_OAI4_", 8 },
- { "$_MUX_", 12 },
- { "$_NMUX_", 10 }
- };
-
- if (cmos_cost && cmos_gate_cost.count(type))
- return cmos_gate_cost.at(type);
-
- if (gate_cost.count(type))
- return gate_cost.at(type);
-
- if (parameters.empty() && design && design->module(type))
+ static const dict<RTLIL::IdString, int>& default_gate_cost() {
+ static const dict<RTLIL::IdString, int> db = {
+ { "$_BUF_", 1 },
+ { "$_NOT_", 2 },
+ { "$_AND_", 4 },
+ { "$_NAND_", 4 },
+ { "$_OR_", 4 },
+ { "$_NOR_", 4 },
+ { "$_ANDNOT_", 4 },
+ { "$_ORNOT_", 4 },
+ { "$_XOR_", 5 },
+ { "$_XNOR_", 5 },
+ { "$_AOI3_", 6 },
+ { "$_OAI3_", 6 },
+ { "$_AOI4_", 7 },
+ { "$_OAI4_", 7 },
+ { "$_MUX_", 4 },
+ { "$_NMUX_", 4 }
+ };
+ return db;
+ }
+
+ static const dict<RTLIL::IdString, int>& cmos_gate_cost() {
+ static const dict<RTLIL::IdString, int> db = {
+ { "$_BUF_", 1 },
+ { "$_NOT_", 2 },
+ { "$_AND_", 6 },
+ { "$_NAND_", 4 },
+ { "$_OR_", 6 },
+ { "$_NOR_", 4 },
+ { "$_ANDNOT_", 6 },
+ { "$_ORNOT_", 6 },
+ { "$_XOR_", 12 },
+ { "$_XNOR_", 12 },
+ { "$_AOI3_", 6 },
+ { "$_OAI3_", 6 },
+ { "$_AOI4_", 8 },
+ { "$_OAI4_", 8 },
+ { "$_MUX_", 12 },
+ { "$_NMUX_", 10 }
+ };
+ return db;
+ }
+
+ dict<RTLIL::IdString, int> mod_cost_cache;
+ const dict<RTLIL::IdString, int> *gate_cost = nullptr;
+ Design *design = nullptr;
+
+ int get(RTLIL::IdString type) const
{
- RTLIL::Module *mod = design->module(type);
+ if (gate_cost && gate_cost->count(type))
+ return gate_cost->at(type);
- if (mod->attributes.count("\\cost"))
- return mod->attributes.at("\\cost").as_int();
+ log_warning("Can't determine cost of %s cell.\n", log_id(type));
+ return 1;
+ }
- dict<RTLIL::IdString, int> local_mod_cost_cache;
- if (mod_cost_cache == nullptr)
- mod_cost_cache = &local_mod_cost_cache;
+ int get(RTLIL::Cell *cell)
+ {
+ if (gate_cost && gate_cost->count(cell->type))
+ return gate_cost->at(cell->type);
- if (mod_cost_cache->count(mod->name))
- return mod_cost_cache->at(mod->name);
+ if (design && design->module(cell->type) && cell->parameters.empty())
+ {
+ RTLIL::Module *mod = design->module(cell->type);
- int module_cost = 1;
- for (auto c : mod->cells())
- module_cost += get_cell_cost(c, mod_cost_cache);
+ if (mod->attributes.count("\\cost"))
+ return mod->attributes.at("\\cost").as_int();
- (*mod_cost_cache)[mod->name] = module_cost;
- return module_cost;
- }
+ if (mod_cost_cache.count(mod->name))
+ return mod_cost_cache.at(mod->name);
- log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters));
- return 1;
-}
+ int module_cost = 1;
+ for (auto c : mod->cells())
+ module_cost += get(c);
-inline int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache, bool cmos_cost)
-{
- return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache, cmos_cost);
-}
+ mod_cost_cache[mod->name] = module_cost;
+ return module_cost;
+ }
+
+ log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters));
+ return 1;
+ }
+};
YOSYS_NAMESPACE_END
diff --git a/kernel/driver.cc b/kernel/driver.cc
index f273057dd..70a97c4b9 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -522,6 +522,12 @@ int main(int argc, char **argv)
if (!backend_command.empty())
run_backend(output_filename, backend_command);
+ yosys_design->check();
+ for (auto it : saved_designs)
+ it.second->check();
+ for (auto it : pushed_designs)
+ it->check();
+
if (!depsfile.empty())
{
FILE *f = fopen(depsfile.c_str(), "wt");
diff --git a/kernel/macc.h b/kernel/macc.h
index 286ce567f..c7595ebc1 100644
--- a/kernel/macc.h
+++ b/kernel/macc.h
@@ -70,9 +70,9 @@ struct Macc
while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])
port.in_b.remove(GetSize(port.in_b)-1);
} else {
- while (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == RTLIL::S0)
+ while (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == State::S0)
port.in_a.remove(GetSize(port.in_a)-1);
- while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == RTLIL::S0)
+ while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == State::S0)
port.in_b.remove(GetSize(port.in_b)-1);
}
@@ -80,9 +80,9 @@ struct Macc
}
for (auto &bit : bit_ports)
- if (bit == RTLIL::S1)
+ if (bit == State::S1)
off = const_add(off, RTLIL::Const(1, width), false, false, width);
- else if (bit != RTLIL::S0)
+ else if (bit != State::S0)
new_bit_ports.append(bit);
if (off.as_bool()) {
@@ -113,10 +113,10 @@ struct Macc
#endif
int num_bits = 0;
- if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 1;
- if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 2;
- if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 4;
- if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 8;
+ if (config_bits[config_cursor++] == State::S1) num_bits |= 1;
+ if (config_bits[config_cursor++] == State::S1) num_bits |= 2;
+ if (config_bits[config_cursor++] == State::S1) num_bits |= 4;
+ if (config_bits[config_cursor++] == State::S1) num_bits |= 8;
int port_a_cursor = 0;
while (port_a_cursor < GetSize(port_a))
@@ -124,12 +124,12 @@ struct Macc
log_assert(config_cursor + 2 + 2*num_bits <= config_width);
port_t this_port;
- this_port.is_signed = config_bits[config_cursor++] == RTLIL::S1;
- this_port.do_subtract = config_bits[config_cursor++] == RTLIL::S1;
+ this_port.is_signed = config_bits[config_cursor++] == State::S1;
+ this_port.do_subtract = config_bits[config_cursor++] == State::S1;
int size_a = 0;
for (int i = 0; i < num_bits; i++)
- if (config_bits[config_cursor++] == RTLIL::S1)
+ if (config_bits[config_cursor++] == State::S1)
size_a |= 1 << i;
this_port.in_a = port_a.extract(port_a_cursor, size_a);
@@ -137,7 +137,7 @@ struct Macc
int size_b = 0;
for (int i = 0; i < num_bits; i++)
- if (config_bits[config_cursor++] == RTLIL::S1)
+ if (config_bits[config_cursor++] == State::S1)
size_b |= 1 << i;
this_port.in_b = port_a.extract(port_a_cursor, size_b);
@@ -166,26 +166,26 @@ struct Macc
num_bits++, max_size /= 2;
log_assert(num_bits < 16);
- config_bits.push_back(num_bits & 1 ? RTLIL::S1 : RTLIL::S0);
- config_bits.push_back(num_bits & 2 ? RTLIL::S1 : RTLIL::S0);
- config_bits.push_back(num_bits & 4 ? RTLIL::S1 : RTLIL::S0);
- config_bits.push_back(num_bits & 8 ? RTLIL::S1 : RTLIL::S0);
+ config_bits.push_back(num_bits & 1 ? State::S1 : State::S0);
+ config_bits.push_back(num_bits & 2 ? State::S1 : State::S0);
+ config_bits.push_back(num_bits & 4 ? State::S1 : State::S0);
+ config_bits.push_back(num_bits & 8 ? State::S1 : State::S0);
for (auto &port : ports)
{
if (GetSize(port.in_a) == 0)
continue;
- config_bits.push_back(port.is_signed ? RTLIL::S1 : RTLIL::S0);
- config_bits.push_back(port.do_subtract ? RTLIL::S1 : RTLIL::S0);
+ config_bits.push_back(port.is_signed ? State::S1 : State::S0);
+ config_bits.push_back(port.do_subtract ? State::S1 : State::S0);
int size_a = GetSize(port.in_a);
for (int i = 0; i < num_bits; i++)
- config_bits.push_back(size_a & (1 << i) ? RTLIL::S1 : RTLIL::S0);
+ config_bits.push_back(size_a & (1 << i) ? State::S1 : State::S0);
int size_b = GetSize(port.in_b);
for (int i = 0; i < num_bits; i++)
- config_bits.push_back(size_b & (1 << i) ? RTLIL::S1 : RTLIL::S0);
+ config_bits.push_back(size_b & (1 << i) ? State::S1 : State::S0);
port_a.append(port.in_a);
port_a.append(port.in_b);
@@ -202,7 +202,7 @@ struct Macc
bool eval(RTLIL::Const &result) const
{
for (auto &bit : result.bits)
- bit = RTLIL::S0;
+ bit = State::S0;
for (auto &port : ports)
{
diff --git a/kernel/register.cc b/kernel/register.cc
index 4f60338e9..1fd1bad1d 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -200,7 +200,7 @@ void Pass::extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Desig
{
std::string arg = args[argidx];
- if (arg.substr(0, 1) == "-")
+ if (arg.compare(0, 1, "-") == 0)
cmd_error(args, argidx, "Unknown option or option in arguments.");
if (!select)
@@ -295,8 +295,6 @@ void Pass::call(RTLIL::Design *design, std::vector<std::string> args)
pass_register[args[0]]->post_execute(state);
while (design->selection_stack.size() > orig_sel_stack_pos)
design->selection_stack.pop_back();
-
- design->check();
}
void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)
@@ -378,8 +376,10 @@ void ScriptPass::run(std::string command, std::string info)
log(" %s\n", command.c_str());
else
log(" %s %s\n", command.c_str(), info.c_str());
- } else
+ } else {
Pass::call(active_design, command);
+ active_design->check();
+ }
}
void ScriptPass::run_script(RTLIL::Design *design, std::string run_from, std::string run_to)
@@ -449,7 +449,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
{
std::string arg = args[argidx];
- if (arg.substr(0, 1) == "-")
+ if (arg.compare(0, 1, "-") == 0)
cmd_error(args, argidx, "Unknown option or option in arguments.");
if (f != NULL)
cmd_error(args, argidx, "Extra filename argument in direct file mode.");
@@ -457,7 +457,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
filename = arg;
if (filename == "<<" && argidx+1 < args.size())
filename += args[++argidx];
- if (filename.substr(0, 2) == "<<") {
+ if (filename.compare(0, 2, "<<") == 0) {
if (Frontend::current_script_file == NULL)
log_error("Unexpected here document '%s' outside of script!\n", filename.c_str());
if (filename.size() <= 2)
@@ -475,7 +475,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
break;
}
size_t indent = buffer.find_first_not_of(" \t\r\n");
- if (indent != std::string::npos && buffer.substr(indent, eot_marker.size()) == eot_marker)
+ if (indent != std::string::npos && buffer.compare(indent, eot_marker.size(), eot_marker) == 0)
break;
last_here_document += buffer;
}
@@ -522,7 +522,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
log_cmd_error("Can't open input file `%s' for reading: %s\n", filename.c_str(), strerror(errno));
for (size_t i = argidx+1; i < args.size(); i++)
- if (args[i].substr(0, 1) == "-")
+ if (args[i].compare(0, 1, "-") == 0)
cmd_error(args, i, "Found option, expected arguments.");
if (argidx+1 < args.size()) {
@@ -573,8 +573,6 @@ void Frontend::frontend_call(RTLIL::Design *design, std::istream *f, std::string
args.push_back(filename);
frontend_register[args[0]]->execute(args, design);
}
-
- design->check();
}
Backend::Backend(std::string name, std::string short_help) :
@@ -614,7 +612,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<st
{
std::string arg = args[argidx];
- if (arg.substr(0, 1) == "-" && arg != "-")
+ if (arg.compare(0, 1, "-") == 0 && arg != "-")
cmd_error(args, argidx, "Unknown option or option in arguments.");
if (f != NULL)
cmd_error(args, argidx, "Extra filename argument in direct file mode.");
@@ -627,7 +625,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<st
filename = arg;
rewrite_filename(filename);
- if (filename.size() > 3 && filename.substr(filename.size()-3) == ".gz") {
+ if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".gz") == 0) {
#ifdef YOSYS_ENABLE_ZLIB
gzip_ostream *gf = new gzip_ostream;
if (!gf->open(filename)) {
@@ -698,8 +696,6 @@ void Backend::backend_call(RTLIL::Design *design, std::ostream *f, std::string f
while (design->selection_stack.size() > orig_sel_stack_pos)
design->selection_stack.pop_back();
-
- design->check();
}
static struct CellHelpMessages {
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index ba8472ec1..fade0bc36 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -47,7 +47,7 @@ RTLIL::Const::Const(std::string str)
for (int i = str.size()-1; i >= 0; i--) {
unsigned char ch = str[i];
for (int j = 0; j < 8; j++) {
- bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
+ bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
ch = ch >> 1;
}
}
@@ -57,7 +57,7 @@ RTLIL::Const::Const(int val, int width)
{
flags = RTLIL::CONST_FLAG_NONE;
for (int i = 0; i < width; i++) {
- bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
+ bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
val = val >> 1;
}
}
@@ -73,7 +73,7 @@ RTLIL::Const::Const(const std::vector<bool> &bits)
{
flags = RTLIL::CONST_FLAG_NONE;
for (auto b : bits)
- this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
+ this->bits.push_back(b ? State::S1 : State::S0);
}
RTLIL::Const::Const(const RTLIL::Const &c)
@@ -106,7 +106,7 @@ bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
bool RTLIL::Const::as_bool() const
{
for (size_t i = 0; i < bits.size(); i++)
- if (bits[i] == RTLIL::S1)
+ if (bits[i] == State::S1)
return true;
return false;
}
@@ -115,9 +115,9 @@ int RTLIL::Const::as_int(bool is_signed) const
{
int32_t ret = 0;
for (size_t i = 0; i < bits.size() && i < 32; i++)
- if (bits[i] == RTLIL::S1)
+ if (bits[i] == State::S1)
ret |= 1 << i;
- if (is_signed && bits.back() == RTLIL::S1)
+ if (is_signed && bits.back() == State::S1)
for (size_t i = bits.size(); i < 32; i++)
ret |= 1 << i;
return ret;
@@ -828,8 +828,8 @@ namespace {
void check()
{
- if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
- cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
+ if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
+ cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
return;
if (cell->type.in("$not", "$pos", "$neg")) {
@@ -940,7 +940,7 @@ namespace {
return;
}
- if (cell->type == "$logic_and" || cell->type == "$logic_or") {
+ if (cell->type.in("$logic_and", "$logic_or")) {
param_bool("\\A_SIGNED");
param_bool("\\B_SIGNED");
port("\\A", param("\\A_WIDTH"));
@@ -2553,8 +2553,8 @@ void RTLIL::Cell::check()
void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
{
- if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
- type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
+ if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
+ type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
return;
if (type == "$mux" || type == "$pmux") {
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 1cfe71473..37b5f984c 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -276,20 +276,24 @@ namespace RTLIL
return std::string(c_str() + pos, len);
}
+ int compare(size_t pos, size_t len, const char* s) const {
+ return strncmp(c_str()+pos, s, len);
+ }
+
bool begins_with(const char* prefix) const {
size_t len = strlen(prefix);
if (size() < len) return false;
- return substr(0, len) == prefix;
+ return compare(0, len, prefix) == 0;
}
bool ends_with(const char* suffix) const {
size_t len = strlen(suffix);
if (size() < len) return false;
- return substr(size()-len) == suffix;
+ return compare(size()-len, len, suffix) == 0;
}
size_t size() const {
- return str().size();
+ return strlen(c_str());
}
bool empty() const {
@@ -788,6 +792,7 @@ public:
RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;
RTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;
RTLIL::SigSpec extract(int offset, int length = 1) const;
+ RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }
void append(const RTLIL::SigSpec &signal);
void append_bit(const RTLIL::SigBit &bit);
@@ -834,6 +839,7 @@ public:
operator std::vector<RTLIL::SigChunk>() const { return chunks(); }
operator std::vector<RTLIL::SigBit>() const { return bits(); }
+ RTLIL::SigBit at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }
unsigned int hash() const { if (!hash_) updhash(); return hash_; };
@@ -1402,7 +1408,7 @@ struct RTLIL::Process : public RTLIL::AttrObject
inline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }
inline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
-inline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? RTLIL::S1 : RTLIL::S0) { }
+inline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }
inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }
inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
diff --git a/kernel/satgen.h b/kernel/satgen.h
index e9f3ecd44..596f522ec 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -1023,7 +1023,7 @@ struct SatGen
std::vector<int> lut;
for (auto bit : cell->getParam("\\LUT").bits)
- lut.push_back(bit == RTLIL::S1 ? ez->CONST_TRUE : ez->CONST_FALSE);
+ lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE);
while (GetSize(lut) < (1 << GetSize(a)))
lut.push_back(ez->CONST_FALSE);
lut.resize(1 << GetSize(a));
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 191b6d5c7..5a53f90fd 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -647,12 +647,12 @@ std::vector<std::string> glob_filename(const std::string &filename_pattern)
void rewrite_filename(std::string &filename)
{
- if (filename.substr(0, 1) == "\"" && filename.substr(GetSize(filename)-1) == "\"")
+ if (filename.compare(0, 1, "\"") == 0 && filename.compare(GetSize(filename)-1, std::string::npos, "\"") == 0)
filename = filename.substr(1, GetSize(filename)-2);
- if (filename.substr(0, 2) == "+/")
+ if (filename.compare(0, 2, "+/") == 0)
filename = proc_share_dirname() + filename.substr(2);
#ifndef _WIN32
- if (filename.substr(0, 2) == "~/")
+ if (filename.compare(0, 2, "~/") == 0)
filename = filename.replace(0, 1, getenv("HOME"));
#endif
}
@@ -895,25 +895,25 @@ void run_frontend(std::string filename, std::string command, std::string *backen
if (command == "auto") {
std::string filename_trim = filename;
- if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".gz")
+ if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".gz") == 0)
filename_trim.erase(filename_trim.size()-3);
- if (filename_trim.size() > 2 && filename_trim.substr(filename_trim.size()-2) == ".v")
+ if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-2, std::string::npos, ".v") == 0)
command = "verilog";
- else if (filename_trim.size() > 2 && filename_trim.substr(filename_trim.size()-3) == ".sv")
+ else if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".sv") == 0)
command = "verilog -sv";
- else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-4) == ".vhd")
+ else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vhd") == 0)
command = "vhdl";
- else if (filename_trim.size() > 4 && filename_trim.substr(filename_trim.size()-5) == ".blif")
+ else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".blif") == 0)
command = "blif";
- else if (filename_trim.size() > 5 && filename_trim.substr(filename_trim.size()-6) == ".eblif")
+ else if (filename_trim.size() > 5 && filename_trim.compare(filename_trim.size()-6, std::string::npos, ".eblif") == 0)
command = "blif";
- else if (filename_trim.size() > 4 && filename_trim.substr(filename_trim.size()-5) == ".json")
+ else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".json") == 0)
command = "json";
- else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".il")
+ else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".il") == 0)
command = "ilang";
- else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".ys")
+ else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".ys") == 0)
command = "script";
- else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-4) == ".tcl")
+ else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".tcl") == 0)
command = "tcl";
else if (filename == "-")
command = "script";
@@ -964,14 +964,18 @@ void run_frontend(std::string filename, std::string command, std::string *backen
command += next_line;
}
handle_label(command, from_to_active, run_from, run_to);
- if (from_to_active)
+ if (from_to_active) {
Pass::call(design, command);
+ design->check();
+ }
}
if (!command.empty()) {
handle_label(command, from_to_active, run_from, run_to);
- if (from_to_active)
+ if (from_to_active) {
Pass::call(design, command);
+ design->check();
+ }
}
}
catch (...) {
@@ -1000,6 +1004,7 @@ void run_frontend(std::string filename, std::string command, std::string *backen
Pass::call(design, vector<string>({command, filename}));
else
Frontend::frontend_call(design, NULL, filename, command);
+ design->check();
}
void run_frontend(std::string filename, std::string command, RTLIL::Design *design)
@@ -1023,17 +1028,17 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig
design = yosys_design;
if (command == "auto") {
- if (filename.size() > 2 && filename.substr(filename.size()-2) == ".v")
+ if (filename.size() > 2 && filename.compare(filename.size()-2, std::string::npos, ".v") == 0)
command = "verilog";
- else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il")
+ else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0)
command = "ilang";
- else if (filename.size() > 4 && filename.substr(filename.size()-4) == ".aig")
+ else if (filename.size() > 4 && filename.compare(filename.size()-4, std::string::npos, ".aig") == 0)
command = "aiger";
- else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".blif")
+ else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".blif") == 0)
command = "blif";
- else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".edif")
+ else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".edif") == 0)
command = "edif";
- else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".json")
+ else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".json") == 0)
command = "json";
else if (filename == "-")
command = "ilang";
@@ -1067,7 +1072,7 @@ static char *readline_cmd_generator(const char *text, int state)
}
for (; it != pass_register.end(); it++) {
- if (it->first.substr(0, len) == text)
+ if (it->first.compare(0, len, text) == 0)
return strdup((it++)->first.c_str());
}
return NULL;
@@ -1089,7 +1094,7 @@ static char *readline_obj_generator(const char *text, int state)
if (design->selected_active_module.empty())
{
for (auto &it : design->modules_)
- if (RTLIL::unescape_id(it.first).substr(0, len) == text)
+ if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
}
else
@@ -1098,19 +1103,19 @@ static char *readline_obj_generator(const char *text, int state)
RTLIL::Module *module = design->modules_.at(design->selected_active_module);
for (auto &it : module->wires_)
- if (RTLIL::unescape_id(it.first).substr(0, len) == text)
+ if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
for (auto &it : module->memories)
- if (RTLIL::unescape_id(it.first).substr(0, len) == text)
+ if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
for (auto &it : module->cells_)
- if (RTLIL::unescape_id(it.first).substr(0, len) == text)
+ if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
for (auto &it : module->processes)
- if (RTLIL::unescape_id(it.first).substr(0, len) == text)
+ if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
}
@@ -1183,6 +1188,7 @@ void shell(RTLIL::Design *design)
design->selection_stack.pop_back();
log_reset_stack();
}
+ design->check();
}
if (command == NULL)
printf("exit\n");
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-17 19:41:34 +0000