diff options
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/celltypes.h | 3 | ||||
| -rw-r--r-- | kernel/rtlil.cc | 8 |
2 files changed, 5 insertions, 6 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index e30ceb8b1..402d6ea76 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -88,7 +88,7 @@ struct CellTypes std::vector<RTLIL::IdString> unary_ops = { "$not", "$pos", "$bu0", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", - "$logic_not", "$slice" + "$logic_not", "$slice", "$lut" }; std::vector<RTLIL::IdString> binary_ops = { @@ -108,7 +108,6 @@ struct CellTypes for (auto type : std::vector<RTLIL::IdString>({"$mux", "$pmux"})) setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, false); - setup_type("$lut", {"\\I"}, {"\\O"}, false); setup_type("$assert", {"\\A", "\\EN"}, {}, false); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 614ea770b..d118b6257 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -615,8 +615,8 @@ namespace { if (cell->type == "$lut") { param("\\LUT"); - port("\\I", param("\\WIDTH")); - port("\\O", 1); + port("\\A", param("\\WIDTH")); + port("\\Y", 1); check_expected(); return; } @@ -1388,8 +1388,8 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R RTLIL::Cell *cell = addCell(name, "$lut"); cell->parameters["\\LUT"] = lut; cell->parameters["\\WIDTH"] = sig_i.size(); - cell->setPort("\\I", sig_i); - cell->setPort("\\O", sig_o); + cell->setPort("\\A", sig_i); + cell->setPort("\\Y", sig_o); return cell; } |