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-rw-r--r--kernel/driver.cc180
-rw-r--r--kernel/register.cc10
-rw-r--r--kernel/register.h9
-rw-r--r--kernel/rtlil.cc19
-rw-r--r--kernel/rtlil.h2
-rw-r--r--kernel/select.cc36
-rw-r--r--kernel/show.cc160
7 files changed, 351 insertions, 65 deletions
diff --git a/kernel/driver.cc b/kernel/driver.cc
index 1dddefdcb..3de16e724 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -20,13 +20,26 @@
#include <stdio.h>
#include <readline/readline.h>
#include <readline/history.h>
+#include <string.h>
+#include <unistd.h>
+#include <dlfcn.h>
#include "kernel/rtlil.h"
#include "kernel/register.h"
#include "kernel/log.h"
-#include <string.h>
-#include <unistd.h>
-#include <dlfcn.h>
+
+bool fgetline(FILE *f, std::string &buffer)
+{
+ buffer = "";
+ char block[4096];
+ while (1) {
+ if (fgets(block, 4096, f) == NULL)
+ return false;
+ buffer += block;
+ if (buffer.size() > 0 && (buffer[buffer.size()-1] == '\n' || buffer[buffer.size()-1] == '\r'))
+ return true;
+ }
+}
static void run_frontend(std::string filename, std::string command, RTLIL::Design *design, std::string *backend_command)
{
@@ -50,9 +63,13 @@ static void run_frontend(std::string filename, std::string command, RTLIL::Desig
f = fopen(filename.c_str(), "r");
if (f == NULL)
log_error("Can't open script file `%s' for reading: %s\n", filename.c_str(), strerror(errno));
- char buffer[4096];
- while (fgets(buffer, 4096, f) != NULL) {
- Pass::call(design, buffer);
+ std::string command;
+ while (fgetline(f, command)) {
+ Pass::call(design, command);
+ design->check();
+ }
+ if (!command.empty()) {
+ Pass::call(design, command);
design->check();
}
if (filename != "-")
@@ -132,10 +149,13 @@ static char **readline_completion(const char *text, int start, int)
return NULL;
}
-static const char *create_prompt(RTLIL::Design *design)
+static const char *create_prompt(RTLIL::Design *design, int recursion_counter)
{
static char buffer[100];
- std::string str = "\nyosys";
+ std::string str = "\n";
+ if (recursion_counter > 1)
+ str += stringf("(%d) ", recursion_counter);
+ str += "yosys";
if (!design->selected_active_module.empty())
str += stringf(" [%s]", design->selected_active_module.c_str());
if (!design->selection_stack.back().full_selection) {
@@ -151,26 +171,29 @@ static const char *create_prompt(RTLIL::Design *design)
static void shell(RTLIL::Design *design)
{
- static bool recursion_detect = false;
+ static int recursion_counter = 0;
- if (recursion_detect) {
- log("Already in interactive shell.\n");
- return;
- }
-
- recursion_detect = true;
+ recursion_counter++;
log_cmd_error_throw = true;
rl_readline_name = "yosys";
rl_attempted_completion_function = readline_completion;
char *command = NULL;
- while ((command = readline(create_prompt(design))) != NULL)
+ while ((command = readline(create_prompt(design, recursion_counter))) != NULL)
{
if (command[strspn(command, " \t\r\n")] == 0)
continue;
add_history(command);
+ char *p = command + strspn(command, " \t\r\n");
+ if (!strncmp(p, "exit", 4)) {
+ p += 4;
+ p += strspn(p, " \t\r\n");
+ if (*p == 0)
+ break;
+ }
+
try {
assert(design->selection_stack.size() == 1);
Pass::call(design, command);
@@ -180,8 +203,10 @@ static void shell(RTLIL::Design *design)
log_reset_stack();
}
}
+ if (command == NULL)
+ printf("exit\n");
- recursion_detect = false;
+ recursion_counter--;
log_cmd_error_throw = false;
}
@@ -216,7 +241,7 @@ struct ShellPass : public Pass {
log("This command is the default action if nothing else has been specified\n");
log("on the command line.\n");
log("\n");
- log("Press Ctrl-D to leave the interactive shell.\n");
+ log("Press Ctrl-D or type 'exit' to leave the interactive shell.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
@@ -225,6 +250,82 @@ struct ShellPass : public Pass {
}
} ShellPass;
+struct ScriptPass : public Pass {
+ ScriptPass() : Pass("script", "execute commands from script file") { }
+ virtual void help() {
+ log("\n");
+ log(" script <filename>\n");
+ log("\n");
+ log("This command executes the yosys commands in the specified file.\n");
+ log("\n");
+ }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+ if (args.size() < 2)
+ log_cmd_error("Missing script file.\n");
+ if (args.size() > 2)
+ extra_args(args, 1, design, false);
+ run_frontend(args[1], "script", design, NULL);
+ }
+} ScriptPass;
+
+#ifdef YOSYS_ENABLE_TCL
+struct TclPass : public Pass {
+ TclPass() : Pass("tcl", "execute a TCL script file") { }
+ virtual void help() {
+ log("\n");
+ log(" tcl <filename>\n");
+ log("\n");
+ log("This command executes the tcl commands in the specified file.\n");
+ log("Use 'yosys cmd' to run the yosys command 'cmd' from tcl.\n");
+ log("\n");
+ log("The tcl command 'yosys -import' can be used to import all yosys\n");
+ log("commands directly as tcl commands to the tcl shell. The yosys\n");
+ log("command 'proc' is wrapped using the tcl command 'procs' in order\n");
+ log("to avoid a name collision with the tcl builting command 'proc'.\n");
+ log("\n");
+ }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+ if (args.size() < 2)
+ log_cmd_error("Missing script file.\n");
+ if (args.size() > 2)
+ extra_args(args, 1, design, false);
+ if (Tcl_EvalFile(yosys_tcl, args[1].c_str()) != TCL_OK)
+ log_cmd_error("TCL interpreter returned an error: %s\n", Tcl_GetStringResult(yosys_tcl));
+ }
+} TclPass;
+
+static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *argv[])
+{
+ std::vector<std::string> args;
+ for (int i = 1; i < argc; i++)
+ args.push_back(argv[i]);
+
+ if (args.size() >= 1 && args[0] == "-import") {
+ for (auto &it : REGISTER_INTERN::pass_register) {
+ std::string tcl_command_name = it.first;
+ if (tcl_command_name == "proc")
+ tcl_command_name = "procs";
+ Tcl_CmdInfo info;
+ if (Tcl_GetCommandInfo(interp, tcl_command_name.c_str(), &info) != 0) {
+ log("[TCL: yosys -import] Command name collision: found pre-existing command `%s' -> skip.\n", it.first.c_str());
+ } else {
+ std::string tcl_script = stringf("proc %s args { yosys %s {*}$args }", tcl_command_name.c_str(), it.first.c_str());
+ Tcl_Eval(interp, tcl_script.c_str());
+ }
+ }
+ return TCL_OK;
+ }
+
+ if (args.size() == 1) {
+ Pass::call(yosys_tcl_design, args[0]);
+ return TCL_OK;
+ }
+
+ Pass::call(yosys_tcl_design, args);
+ return TCL_OK;
+}
+#endif
+
int main(int argc, char **argv)
{
std::string frontend_command = "auto";
@@ -233,10 +334,16 @@ int main(int argc, char **argv)
std::vector<void*> loaded_modules;
std::string output_filename = "";
std::string scriptfile = "";
+ bool scriptfile_tcl = false;
bool got_output_filename = false;
+#ifdef YOSYS_ENABLE_TCL
+ yosys_tcl = Tcl_CreateInterp();
+ Tcl_CreateCommand(yosys_tcl, "yosys", tcl_yosys_cmd, NULL, NULL);
+#endif
+
int opt;
- while ((opt = getopt(argc, argv, "Sm:f:b:o:p:l:qts:")) != -1)
+ while ((opt = getopt(argc, argv, "Sm:f:b:o:p:l:qts:c:")) != -1)
{
switch (opt)
{
@@ -284,10 +391,15 @@ int main(int argc, char **argv)
break;
case 's':
scriptfile = optarg;
+ scriptfile_tcl = false;
+ break;
+ case 'c':
+ scriptfile = optarg;
+ scriptfile_tcl = true;
break;
default:
fprintf(stderr, "\n");
- fprintf(stderr, "Usage: %s [-S] [-q] [-t] [-l logfile] [-o <outfile>] [-f <frontend>] [-s <scriptfile>]\n", argv[0]);
+ fprintf(stderr, "Usage: %s [-S] [-q] [-t] [-l logfile] [-o <outfile>] [-f <frontend>] [{-s|-c} <scriptfile>]\n", argv[0]);
fprintf(stderr, " %*s[-p <pass> [-p ..]] [-b <backend>] [-m <module_file>] [<infile> [..]]\n", int(strlen(argv[0])+1), "");
fprintf(stderr, "\n");
fprintf(stderr, " -q\n");
@@ -311,6 +423,9 @@ int main(int argc, char **argv)
fprintf(stderr, " -s scriptfile\n");
fprintf(stderr, " execute the commands in the script file\n");
fprintf(stderr, "\n");
+ fprintf(stderr, " -c tcl_scriptfile\n");
+ fprintf(stderr, " execute the commands in the tcl script file (see 'help tcl' for details)\n");
+ fprintf(stderr, "\n");
fprintf(stderr, " -p command\n");
fprintf(stderr, " execute the commands\n");
fprintf(stderr, "\n");
@@ -366,6 +481,10 @@ int main(int argc, char **argv)
design->selection_stack.push_back(RTLIL::Selection());
log_push();
+#ifdef YOSYS_ENABLE_TCL
+ yosys_tcl_design = design;
+#endif
+
if (optind == argc && passes_commands.size() == 0 && scriptfile.empty()) {
if (!got_output_filename)
backend_command = "";
@@ -375,8 +494,17 @@ int main(int argc, char **argv)
while (optind < argc)
run_frontend(argv[optind++], frontend_command, design, output_filename == "-" ? &backend_command : NULL);
- if (!scriptfile.empty())
- run_frontend(scriptfile, "script", design, output_filename == "-" ? &backend_command : NULL);
+ if (!scriptfile.empty()) {
+ if (scriptfile_tcl) {
+#ifdef YOSYS_ENABLE_TCL
+ if (Tcl_EvalFile(yosys_tcl, scriptfile.c_str()) != TCL_OK)
+ log_error("TCL interpreter returned an error: %s\n", Tcl_GetStringResult(yosys_tcl));
+#else
+ log_error("Can't exectue TCL script: this version of yosys is not built with TCL support enabled.\n");
+#endif
+ } else
+ run_frontend(scriptfile, "script", design, output_filename == "-" ? &backend_command : NULL);
+ }
for (auto it = passes_commands.begin(); it != passes_commands.end(); it++)
run_pass(*it, design);
@@ -386,6 +514,10 @@ int main(int argc, char **argv)
delete design;
+#ifdef YOSYS_ENABLE_TCL
+ yosys_tcl_design = NULL;
+#endif
+
log("\nREADY.\n");
log_pop();
@@ -400,6 +532,10 @@ int main(int argc, char **argv)
for (auto mod : loaded_modules)
dlclose(mod);
+#ifdef YOSYS_ENABLE_TCL
+ Tcl_DeleteInterp(yosys_tcl);
+#endif
+
return 0;
}
diff --git a/kernel/register.cc b/kernel/register.cc
index 1dd608754..bfd51feb1 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -27,6 +27,11 @@
using namespace REGISTER_INTERN;
#define MAX_REG_COUNT 1000
+#ifdef YOSYS_ENABLE_TCL
+Tcl_Interp *yosys_tcl = NULL;
+RTLIL::Design *yosys_tcl_design = NULL;
+#endif
+
namespace REGISTER_INTERN
{
int raw_register_count = 0;
@@ -109,9 +114,6 @@ void Pass::cmd_error(const std::vector<std::string> &args, size_t argidx, std::s
msg.c_str(), command_text.c_str(), error_pos, "");
}
-// implemented in kernel/select.cc
-extern void handle_extra_select_args(Pass *pass, std::vector<std::string> args, size_t argidx, RTLIL::Design *design);
-
void Pass::extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Design *design, bool select)
{
for (; argidx < args.size(); argidx++)
@@ -124,7 +126,7 @@ void Pass::extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Desig
if (!select)
cmd_error(args, argidx, "Extra argument.");
- handle_extra_select_args(this, args, argidx, design);
+ handle_extra_select_args(this, args, argidx, args.size(), design);
break;
}
cmd_log_args(args);
diff --git a/kernel/register.h b/kernel/register.h
index a817d8c64..2f664e7c1 100644
--- a/kernel/register.h
+++ b/kernel/register.h
@@ -26,6 +26,12 @@
#include <vector>
#include <map>
+#ifdef YOSYS_ENABLE_TCL
+#include <tcl.h>
+extern Tcl_Interp *yosys_tcl;
+extern RTLIL::Design *yosys_tcl_design;
+#endif
+
struct Pass
{
std::string pass_name, short_help;
@@ -77,6 +83,9 @@ struct Backend : Pass
static void backend_call(RTLIL::Design *design, FILE *f, std::string filename, std::vector<std::string> args);
};
+// implemented in kernel/select.cc
+extern void handle_extra_select_args(Pass *pass, std::vector<std::string> args, size_t argidx, size_t args_size, RTLIL::Design *design);
+
namespace REGISTER_INTERN {
extern int raw_register_count;
extern bool raw_register_done;
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index c97e2e455..b0dcfe428 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -18,6 +18,7 @@
*/
#include "kernel/rtlil.h"
+#include "kernel/log.h"
#include <assert.h>
#include <algorithm>
@@ -257,13 +258,12 @@ RTLIL::Module::~Module()
RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
{
- assert(!"Called derive() from module base class.");
- abort();
+ log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
}
void RTLIL::Module::update_auto_wires(std::map<RTLIL::IdString, int>)
{
- assert(!"Called update_auto_wires() from module base class.");
+ log_error("Module `%s' has automatic wires bu no HDL backend to handle it!\n", id2cstr(name));
}
size_t RTLIL::Module::count_id(RTLIL::IdString id)
@@ -566,7 +566,7 @@ void RTLIL::SigSpec::optimize()
check();
}
-static bool compare_sigchunks(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b)
+bool RTLIL::SigChunk::compare(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b)
{
if (a.wire != b.wire) {
if (a.wire == NULL || b.wire == NULL)
@@ -583,14 +583,21 @@ static bool compare_sigchunks(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b
return a.data.bits < b.data.bits;
}
+void RTLIL::SigSpec::sort()
+{
+ expand();
+ std::sort(chunks.begin(), chunks.end(), RTLIL::SigChunk::compare);
+ optimize();
+}
+
void RTLIL::SigSpec::sort_and_unify()
{
expand();
- std::sort(chunks.begin(), chunks.end(), compare_sigchunks);
+ std::sort(chunks.begin(), chunks.end(), RTLIL::SigChunk::compare);
for (size_t i = 1; i < chunks.size(); i++) {
RTLIL::SigChunk &ch1 = chunks[i-1];
RTLIL::SigChunk &ch2 = chunks[i];
- if (!compare_sigchunks(ch1, ch2) && !compare_sigchunks(ch2, ch1)) {
+ if (!RTLIL::SigChunk::compare(ch1, ch2) && !RTLIL::SigChunk::compare(ch2, ch1)) {
chunks.erase(chunks.begin()+i);
width -= chunks[i].width;
i--;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index a0d7a1a37..fe88182fa 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -277,6 +277,7 @@ struct RTLIL::SigChunk {
bool operator <(const RTLIL::SigChunk &other) const;
bool operator ==(const RTLIL::SigChunk &other) const;
bool operator !=(const RTLIL::SigChunk &other) const;
+ static bool compare(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b);
};
struct RTLIL::SigSpec {
@@ -291,6 +292,7 @@ struct RTLIL::SigSpec {
SigSpec(RTLIL::State bit, int width = 1);
void expand();
void optimize();
+ void sort();
void sort_and_unify();
void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);
void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;
diff --git a/kernel/select.cc b/kernel/select.cc
index a6e675c88..fa1c3db02 100644
--- a/kernel/select.cc
+++ b/kernel/select.cc
@@ -346,8 +346,18 @@ static void select_op_expand(RTLIL::Design *design, std::string arg, char mode)
size_t endpos = arg.find(':', pos);
if (endpos == std::string::npos)
endpos = arg.size();
- if (int(endpos) > pos)
- limits.insert(RTLIL::escape_id(arg.substr(pos, endpos-pos)));
+ if (int(endpos) > pos) {
+ std::string str = arg.substr(pos, endpos-pos);
+ if (str[0] == '@') {
+ str = RTLIL::escape_id(str.substr(1));
+ if (design->selection_vars.count(str) > 0) {
+ for (auto i1 : design->selection_vars.at(str).selected_members)
+ for (auto i2 : i1.second)
+ limits.insert(i2);
+ }
+ } else
+ limits.insert(RTLIL::escape_id(str));
+ }
pos = endpos;
}
}
@@ -471,7 +481,8 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
select_op_expand(design, arg, 'o');
} else
log_cmd_error("Unknown selection operator '%s'.\n", arg.c_str());
- select_filter_active_mod(design, work_stack.back());
+ if (work_stack.size() >= 1)
+ select_filter_active_mod(design, work_stack.back());
return;
}
@@ -585,20 +596,27 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
select_filter_active_mod(design, work_stack.back());
}
-// used in kernel/register.cc
-void handle_extra_select_args(Pass *pass, std::vector<std::string> args, size_t argidx, RTLIL::Design *design)
+// used in kernel/register.cc and maybe other locations, extern decl. in register.h
+void handle_extra_select_args(Pass *pass, std::vector<std::string> args, size_t argidx, size_t args_size, RTLIL::Design *design)
{
work_stack.clear();
- for (; argidx < args.size(); argidx++) {
- if (args[argidx].substr(0, 1) == "-")
- pass->cmd_error(args, argidx, "Unexpected option in selection arguments.");
+ for (; argidx < args_size; argidx++) {
+ if (args[argidx].substr(0, 1) == "-") {
+ if (pass != NULL)
+ pass->cmd_error(args, argidx, "Unexpected option in selection arguments.");
+ else
+ log_cmd_error("Unexpected option in selection arguments.");
+ }
select_stmt(design, args[argidx]);
}
while (work_stack.size() > 1) {
select_op_union(design, work_stack.front(), work_stack.back());
work_stack.pop_back();
}
- design->selection_stack.push_back(work_stack.back());
+ if (work_stack.size() > 0)
+ design->selection_stack.push_back(work_stack.back());
+ else
+ design->selection_stack.push_back(RTLIL::Selection(false));
}
struct SelectPass : public Pass {
diff --git a/kernel/show.cc b/kernel/show.cc
index 321d9e2e0..fd703dd53 100644
--- a/kernel/show.cc
+++ b/kernel/show.cc
@@ -36,7 +36,7 @@ struct ShowWorker
std::map<RTLIL::IdString, int> autonames;
int single_idx_count;
- struct net_conn { std::set<std::string> in, out; int bits; };
+ struct net_conn { std::set<std::string> in, out; int bits; std::string color; };
std::map<std::string, net_conn> net_conn_map;
FILE *f;
@@ -47,6 +47,9 @@ struct ShowWorker
bool stretchIO;
int page_counter;
+ const std::vector<std::pair<std::string, RTLIL::Selection>> &color_selections;
+ const std::vector<std::pair<std::string, RTLIL::Selection>> &label_selections;
+
uint32_t xorshift32(uint32_t x) {
x ^= x << 13;
x ^= x >> 17;
@@ -61,6 +64,40 @@ struct ShowWorker
return stringf("colorscheme=\"dark28\", color=\"%d\", fontcolor=\"%d\"", currentColor%8+1);
}
+ std::string nextColor(std::string presetColor)
+ {
+ if (presetColor.empty())
+ return nextColor();
+ return presetColor;
+ }
+
+ std::string nextColor(RTLIL::SigSpec sig, std::string defaultColor)
+ {
+ sig.sort_and_unify();
+ for (auto &c : sig.chunks) {
+ if (c.wire != NULL)
+ for (auto &s : color_selections)
+ if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0)
+ return stringf("color=\"%s\", fontcolor=\"%d\"", s.first.c_str(), s.first.c_str());
+ }
+ return defaultColor;
+ }
+
+ std::string nextColor(RTLIL::SigSig &conn, std::string defaultColor)
+ {
+ return nextColor(conn.first, nextColor(conn.second, defaultColor));
+ }
+
+ std::string nextColor(RTLIL::SigSpec &sig)
+ {
+ return nextColor(sig, nextColor());
+ }
+
+ std::string nextColor(RTLIL::SigSig &conn)
+ {
+ return nextColor(conn, nextColor());
+ }
+
std::string widthLabel(int bits)
{
if (bits <= 1)
@@ -145,10 +182,12 @@ struct ShowWorker
label_string += stringf("<s%d> %d:%d - %d:%d |", i, pos, pos-c.width+1, c.offset+c.width-1, c.offset);
net_conn_map[net].in.insert(stringf("x%d:s%d", idx, i));
net_conn_map[net].bits = c.width;
+ net_conn_map[net].color = nextColor(c, net_conn_map[net].color);
} else {
label_string += stringf("<s%d> %d:%d - %d:%d |", i, c.offset+c.width-1, c.offset, pos, pos-c.width+1);
net_conn_map[net].out.insert(stringf("x%d:s%d", idx, i));
net_conn_map[net].bits = c.width;
+ net_conn_map[net].color = nextColor(c, net_conn_map[net].color);
}
pos -= c.width;
}
@@ -158,9 +197,9 @@ struct ShowWorker
if (!port.empty()) {
currentColor = xorshift32(currentColor);
if (driver)
- code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), idx, nextColor().c_str(), widthLabel(sig.width).c_str());
+ code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), idx, nextColor(sig).c_str(), widthLabel(sig.width).c_str());
else
- code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor().c_str(), widthLabel(sig.width).c_str());
+ code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.width).c_str());
}
if (node != NULL)
*node = stringf("x%d", idx);
@@ -173,6 +212,7 @@ struct ShowWorker
else
net_conn_map[net].out.insert(port);
net_conn_map[net].bits = sig.width;
+ net_conn_map[net].color = nextColor(sig, net_conn_map[net].color);
}
if (node != NULL)
*node = net;
@@ -202,8 +242,9 @@ struct ShowWorker
if (it.second->port_input || it.second->port_output)
shape = "octagon";
if (it.first[0] == '\\') {
- fprintf(f, "n%d [ shape=%s, label=\"%s\" ];\n",
- id2num(it.first), shape, escape(it.first));
+ fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n",
+ id2num(it.first), shape, escape(it.first),
+ nextColor(RTLIL::SigSpec(it.second), "color=\"black\"").c_str());
if (it.second->port_input)
all_sources.insert(stringf("n%d", id2num(it.first)));
else if (it.second->port_output)
@@ -294,10 +335,12 @@ struct ShowWorker
if (left_node[0] == 'x' && right_node[0] == 'x') {
currentColor = xorshift32(currentColor);
- fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", left_node.c_str(), right_node.c_str(), nextColor().c_str(), widthLabel(conn.first.width).c_str());
+ fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", left_node.c_str(), right_node.c_str(), nextColor(conn).c_str(), widthLabel(conn.first.width).c_str());
} else {
net_conn_map[right_node].bits = conn.first.width;
+ net_conn_map[right_node].color = nextColor(conn, net_conn_map[right_node].color);
net_conn_map[left_node].bits = conn.first.width;
+ net_conn_map[left_node].color = nextColor(conn, net_conn_map[left_node].color);
if (left_node[0] == 'x') {
net_conn_map[right_node].in.insert(left_node);
} else if (right_node[0] == 'x') {
@@ -315,7 +358,7 @@ struct ShowWorker
currentColor = xorshift32(currentColor);
if (wires_on_demand.count(it.first) > 0) {
if (it.second.in.size() == 1 && it.second.out.size() == 1) {
- fprintf(f, "%s:e -> %s:w [%s, %s];\n", it.second.in.begin()->c_str(), it.second.out.begin()->c_str(), nextColor().c_str(), widthLabel(it.second.bits).c_str());
+ fprintf(f, "%s:e -> %s:w [%s, %s];\n", it.second.in.begin()->c_str(), it.second.out.begin()->c_str(), nextColor(it.second.color).c_str(), widthLabel(it.second.bits).c_str());
continue;
}
if (it.second.in.size() == 0 || it.second.out.size() == 0)
@@ -324,16 +367,19 @@ struct ShowWorker
fprintf(f, "%s [ shape=point ];\n", it.first.c_str());
}
for (auto &it2 : it.second.in)
- fprintf(f, "%s:e -> %s:w [%s, %s];\n", it2.c_str(), it.first.c_str(), nextColor().c_str(), widthLabel(it.second.bits).c_str());
+ fprintf(f, "%s:e -> %s:w [%s, %s];\n", it2.c_str(), it.first.c_str(), nextColor(it.second.color).c_str(), widthLabel(it.second.bits).c_str());
for (auto &it2 : it.second.out)
- fprintf(f, "%s:e -> %s:w [%s, %s];\n", it.first.c_str(), it2.c_str(), nextColor().c_str(), widthLabel(it.second.bits).c_str());
+ fprintf(f, "%s:e -> %s:w [%s, %s];\n", it.first.c_str(), it2.c_str(), nextColor(it.second.color).c_str(), widthLabel(it.second.bits).c_str());
}
fprintf(f, "};\n");
}
- ShowWorker(FILE *f, RTLIL::Design *design, std::vector<RTLIL::Design*> &libs, uint32_t colorSeed, bool genWidthLabels, bool stretchIO) :
- f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels), stretchIO(stretchIO)
+ ShowWorker(FILE *f, RTLIL::Design *design, std::vector<RTLIL::Design*> &libs, uint32_t colorSeed, bool genWidthLabels, bool stretchIO,
+ const std::vector<std::pair<std::string, RTLIL::Selection>> &color_selections,
+ const std::vector<std::pair<std::string, RTLIL::Selection>> &label_selections) :
+ f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels), stretchIO(stretchIO),
+ color_selections(color_selections), label_selections(label_selections)
{
ct.setup_internals();
ct.setup_internals_mem();
@@ -352,8 +398,12 @@ struct ShowWorker
if (!design->selected_module(module->name))
continue;
if (design->selected_whole_module(module->name)) {
+ if (module->attributes.count("\\placeholder") > 0) {
+ log("Skipping placeholder module %s.\n", id2cstr(module->name));
+ continue;
+ } else
if (module->cells.empty() && module->connections.empty()) {
- log("Skipping skeletton module %s.\n", id2cstr(module->name));
+ log("Skipping empty module %s.\n", id2cstr(module->name));
continue;
} else
log("Dumping module %s to page %d.\n", id2cstr(module->name), ++page_counter);
@@ -373,10 +423,14 @@ struct ShowPass : public Pass {
log(" show [options] [selection]\n");
log("\n");
log("Create a graphviz DOT file for the selected part of the design and compile it\n");
- log("to a postscript file.\n");
+ log("to a graphics file (usually SVG or PostScript).\n");
+ log("\n");
+ log(" -viewer <viewer>\n");
+ log(" Run the specified command with the graphics file as parameter.\n");
log("\n");
- log(" -viewer <command>\n");
- log(" Also run the specified command with the postscript file as parameter.\n");
+ log(" -format <format>\n");
+ log(" Generate a graphics file in the specified format.\n");
+ log(" Usually <format> is 'svg' or 'ps'.\n");
log("\n");
log(" -lib <verilog_or_ilang_file>\n");
log(" Use the specified library file for determining whether cell ports are\n");
@@ -386,6 +440,11 @@ struct ShowPass : public Pass {
log(" -prefix <prefix>\n");
log(" generate <prefix>.dot and <prefix>.ps instead of yosys-show.{dot,ps}\n");
log("\n");
+ log(" -color <color> <wire>\n");
+ log(" assign the specified color to the specified wire. The object can be\n");
+ log(" a single selection wildcard expressions or a saved set of objects in\n");
+ log(" the @<name> syntax (see \"help select\" for details).\n");
+ log("\n");
log(" -colors <seed>\n");
log(" Randomly assign colors to the wires. The integer argument is the seed\n");
log(" for the random number generator. Change the seed value if the colored\n");
@@ -398,7 +457,11 @@ struct ShowPass : public Pass {
log(" stretch the graph so all inputs are on the left side and all outputs\n");
log(" (including inout ports) are on the right side.\n");
log("\n");
- log("The generated output files are `yosys-show.dot' and `yosys-show.ps'.\n");
+ log("When no <format> is specified, SVG is used. When no <format> and <viewer> is\n");
+ log("specified, 'yosys-svgviewer' is used to display the schematic.\n");
+ log("\n");
+ log("The generated output files are 'yosys-show.dot' and 'yosys-show.<format>',\n");
+ log("unless another prefix is specified using -prefix <prefix>.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
@@ -406,6 +469,10 @@ struct ShowPass : public Pass {
log_header("Generating Graphviz representation of design.\n");
log_push();
+ std::vector<std::pair<std::string, RTLIL::Selection>> color_selections;
+ std::vector<std::pair<std::string, RTLIL::Selection>> label_selections;
+
+ std::string format;
std::string viewer_exe;
std::string prefix = "yosys-show";
std::vector<std::string> libfiles;
@@ -430,10 +497,32 @@ struct ShowPass : public Pass {
prefix = args[++argidx];
continue;
}
+ if (arg == "-color" && argidx+2 < args.size()) {
+ std::pair<std::string, RTLIL::Selection> data;
+ data.first = args[++argidx], argidx++;
+ handle_extra_select_args(this, args, argidx, argidx+1, design);
+ data.second = design->selection_stack.back();
+ design->selection_stack.pop_back();
+ color_selections.push_back(data);
+ continue;
+ }
+ if (arg == "-label" && argidx+2 < args.size() && false) {
+ std::pair<std::string, RTLIL::Selection> data;
+ data.first = args[++argidx], argidx++;
+ handle_extra_select_args(this, args, argidx, argidx+1, design);
+ data.second = design->selection_stack.back();
+ design->selection_stack.pop_back();
+ label_selections.push_back(data);
+ continue;
+ }
if (arg == "-colors" && argidx+1 < args.size()) {
colorSeed = atoi(args[++argidx].c_str());
continue;
}
+ if (arg == "-format" && argidx+1 < args.size()) {
+ format = args[++argidx];
+ continue;
+ }
if (arg == "-width") {
flag_width= true;
continue;
@@ -446,6 +535,20 @@ struct ShowPass : public Pass {
}
extra_args(args, argidx, design);
+ if (format != "ps") {
+ int modcount = 0;
+ for (auto &mod_it : design->modules) {
+ if (mod_it.second->attributes.count("\\placeholder") > 0)
+ continue;
+ if (mod_it.second->cells.empty() && mod_it.second->connections.empty())
+ continue;
+ if (design->selected_module(mod_it.first))
+ modcount++;
+ }
+ if (modcount > 1)
+ log_cmd_error("For formats different than 'ps' only one module must be selected.\n");
+ }
+
for (auto filename : libfiles) {
FILE *f = fopen(filename.c_str(), "rt");
if (f == NULL)
@@ -460,33 +563,42 @@ struct ShowPass : public Pass {
log_header("Continuing show pass.\n");
std::string dot_file = stringf("%s.dot", prefix.c_str());
- std::string ps_file = stringf("%s.ps", prefix.c_str());
+ std::string out_file = stringf("%s.%s", prefix.c_str(), format.empty() ? "svg" : format.c_str());
log("Writing dot description to `%s'.\n", dot_file.c_str());
FILE *f = fopen(dot_file.c_str(), "w");
- if (f == NULL)
+ if (f == NULL) {
+ for (auto lib : libs)
+ delete lib;
log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str());
- ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_stretch);
+ }
+ ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_stretch, color_selections, label_selections);
fclose(f);
+ for (auto lib : libs)
+ delete lib;
+
if (worker.page_counter == 0)
log_cmd_error("Nothing there to show.\n");
- std::string cmd = stringf("dot -Tps -o '%s' '%s'", ps_file.c_str(), dot_file.c_str());
+ std::string cmd = stringf("dot -T%s -o '%s' '%s'", format.empty() ? "svg" : format.c_str(), out_file.c_str(), dot_file.c_str());
log("Exec: %s\n", cmd.c_str());
if (system(cmd.c_str()) != 0)
log_cmd_error("Shell command failed!\n");
if (!viewer_exe.empty()) {
- cmd = stringf("%s '%s' &", viewer_exe.c_str(), ps_file.c_str());
+ cmd = stringf("%s '%s' &", viewer_exe.c_str(), out_file.c_str());
+ log("Exec: %s\n", cmd.c_str());
+ if (system(cmd.c_str()) != 0)
+ log_cmd_error("Shell command failed!\n");
+ } else
+ if (format.empty()) {
+ cmd = stringf("fuser -s '%s' || yosys-svgviewer '%s' &", out_file.c_str(), out_file.c_str());
log("Exec: %s\n", cmd.c_str());
if (system(cmd.c_str()) != 0)
log_cmd_error("Shell command failed!\n");
}
- for (auto lib : libs)
- delete lib;
-
log_pop();
}
} ShowPass;
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-05 11:52:55 +0000