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Diffstat (limited to 'manual/APPNOTE_010_Verilog_to_BLIF.tex')
-rw-r--r-- | manual/APPNOTE_010_Verilog_to_BLIF.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/APPNOTE_010_Verilog_to_BLIF.tex b/manual/APPNOTE_010_Verilog_to_BLIF.tex index 0ecdf6194..5b1c0c359 100644 --- a/manual/APPNOTE_010_Verilog_to_BLIF.tex +++ b/manual/APPNOTE_010_Verilog_to_BLIF.tex @@ -438,7 +438,7 @@ design to fit a certain need without actually touching the RTL code. \bibitem{yosys} Clifford Wolf. The Yosys Open SYnthesis Suite. \\ -\url{http://www.clifford.at/yosys/} +\url{http://yosyshq.net/yosys/} \bibitem{bigsim} yosys-bigsim, a collection of real-world Verilog designs for regression testing purposes. \\ |