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Diffstat (limited to 'manual/APPNOTE_012_Verilog_to_BTOR.tex')
| -rw-r--r-- | manual/APPNOTE_012_Verilog_to_BTOR.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/APPNOTE_012_Verilog_to_BTOR.tex b/manual/APPNOTE_012_Verilog_to_BTOR.tex index 1bc277876..ebaa3e420 100644 --- a/manual/APPNOTE_012_Verilog_to_BTOR.tex +++ b/manual/APPNOTE_012_Verilog_to_BTOR.tex @@ -411,7 +411,7 @@ verification benchmarks with or without memories from Verilog designs. \bibitem{yosys} Clifford Wolf. The Yosys Open SYnthesis Suite. \\ -\url{http://www.clifford.at/yosys/} +\url{http://yosyshq.net/yosys/} \bibitem{boolector} Robert Brummayer and Armin Biere, Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays\\ |