diff options
Diffstat (limited to 'manual/CHAPTER_Eval/or1200.prj')
| -rw-r--r-- | manual/CHAPTER_Eval/or1200.prj | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/manual/CHAPTER_Eval/or1200.prj b/manual/CHAPTER_Eval/or1200.prj new file mode 100644 index 000000000..9496874e0 --- /dev/null +++ b/manual/CHAPTER_Eval/or1200.prj @@ -0,0 +1,37 @@ +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_spram.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_reg2mem.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_mem2reg.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dpram.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_amultp2_32x32.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_wbmux.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_sprs.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_rf.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_operandmuxes.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_mult_mac.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_lsu.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_immu_tlb.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_if.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_tag.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_ram.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_fsm.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_genpc.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_freeze.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_fpu.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_except.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dmmu_tlb.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ctrl.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_cfgr.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_alu.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_wb_biu.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_tt.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_sb.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_qmem_top.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_pm.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_pic.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_immu_top.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_top.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_du.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dmmu_top.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dc_top.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_cpu.v" +verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_top.v" |