diff options
Diffstat (limited to 'manual/CHAPTER_Overview.tex')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index be37d8d39..83cfa5cc4 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -184,12 +184,22 @@ may hold important information for Yosys developers can be used without disturbing external tools. For example the Verilog backend assigns names in the form {\tt \_{\it integer}\_}. \end{itemize} -In order to avoid programming errors, the RTLIL data structures check if all -identifiers start with either a backslash or a dollar sign and generate a -runtime error if this rule is violated. +Whitespace and control characters (any character with an ASCII code 32 or less) are not allowed +in RTLIL identifiers; most frontends and backends cannot support these characters in identifiers. + +In order to avoid programming errors, the RTLIL data structures check if all identifiers start +with either a backslash or a dollar sign, and contain no whitespace or control characters. +Violating these rules results in a runtime error. All RTLIL identifiers are case sensitive. +Some transformations, such as flattening, may have to change identifiers provided by the user +to avoid name collisions. When that happens, attribute ``{\tt hdlname}`` is attached to the object +with the changed identifier. This attribute contains one name (if emitted directly by the frontend, +or is a result of disambiguation) or multiple names separated by spaces (if a result of flattening). +All names specified in the ``{\tt hdlname}`` attribute are public and do not include the leading +``\textbackslash``. + \subsection{RTLIL::Design and RTLIL::Module} The RTLIL::Design object is basically just a container for RTLIL::Module objects. In addition to |