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Diffstat (limited to 'manual/command-reference-manual.tex')
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1 files changed, 638 insertions, 152 deletions
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index 8335d582c..644f81d95 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -22,11 +22,11 @@ library to a target architecture. if no -script parameter is given, the following scripts are used: - for -liberty without -constr: + for -liberty/-genlib without -constr: strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put - for -liberty with -constr: + for -liberty/-genlib with -constr: strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p @@ -49,10 +49,10 @@ library to a target architecture. use different default scripts that are slightly faster (at the cost of output quality): - for -liberty without -constr: + for -liberty/-genlib without -constr: strash; dretime; map {D} - for -liberty with -constr: + for -liberty/-genlib with -constr: strash; dretime; map {D}; buffer; upsize {D}; dnsize {D}; stime -p @@ -69,8 +69,13 @@ library to a target architecture. generate netlists for the specified cell library (using the liberty file format). + -genlib <file> + generate netlists for the specified cell library (using the SIS Genlib + file format). + -constr <file> - pass this file with timing constraints to ABC. use with -liberty. + pass this file with timing constraints to ABC. + use with -liberty/-genlib. a constr file contains two lines: set_driving_cell <cell_name> @@ -167,7 +172,7 @@ library to a target architecture. preserve naming by an equivalence check between the original and post-ABC netlists (experimental). -When neither -liberty nor -lut is used, the Yosys standard cell library is +When no target cell library is specified the Yosys standard cell library is loaded into ABC before the ABC script is executed. Note that this is a logic optimization pass within Yosys that is calling ABC @@ -666,6 +671,14 @@ Convert modules into blackbox modules (remove contents and set the blackbox module attribute). \end{lstlisting} +\section{bmuxmap -- transform \$bmux cells to trees of \$mux cells} +\label{cmd:bmuxmap} +\begin{lstlisting}[numbers=left,frame=single] + bmuxmap [selection] + +This pass transforms $bmux cells to trees of $mux cells. +\end{lstlisting} + \section{bugpoint -- minimize testcases} \label{cmd:bugpoint} \begin{lstlisting}[numbers=left,frame=single] @@ -866,6 +879,16 @@ When commands are separated using the ';;;' token, this command will be executed in -purge mode between the commands. \end{lstlisting} +\section{clean\_zerowidth -- clean zero-width connections from the design} +\label{cmd:clean_zerowidth} +\begin{lstlisting}[numbers=left,frame=single] + clean_zerowidth [selection] + +Fixes the selected cells and processes to contain no zero-width connections. +Depending on the cell type, this may be implemented by removing the connection, +widening it to 1-bit, or removing the cell altogether. +\end{lstlisting} + \section{clk2fflogic -- convert clocked FFs to generic \$ff cells} \label{cmd:clk2fflogic} \begin{lstlisting}[numbers=left,frame=single] @@ -1118,6 +1141,14 @@ selected wires, thus 'deleting' module ports. "Demote" inout ports to input or output ports, if possible. \end{lstlisting} +\section{demuxmap -- transform \$demux cells to \$eq + \$mux cells} +\label{cmd:demuxmap} +\begin{lstlisting}[numbers=left,frame=single] + demuxmap [selection] + +This pass transforms $demux cells to a bunch of equality comparisons. +\end{lstlisting} + \section{design -- save, restore and reset current design} \label{cmd:design} \begin{lstlisting}[numbers=left,frame=single] @@ -2191,6 +2222,133 @@ one-hot encoding and binary encoding is supported. .map <old_bitpattern> <new_bitpattern> \end{lstlisting} +\section{fst2tb -- generate testbench out of fst file} +\label{cmd:fst2tb} +\begin{lstlisting}[numbers=left,frame=single] + fst2tb [options] [top-level] + +This command generates testbench for the circuit using the given top-level module +and simulus signal from FST file + + -tb <name> + generated testbench name. + files <name>.v and <name>.txt are created as result. + + -r <filename> + read simulation FST file + + -clock <portname> + name of top-level clock input + + -clockn <portname> + name of top-level clock input (inverse polarity) + + -scope <name> + scope of simulation top model + + -start <time> + start co-simulation in arbitary time (default 0) + + -stop <time> + stop co-simulation in arbitary time (default END) + + -n <integer> + number of clock cycles to simulate (default: 20) +\end{lstlisting} + +\section{gatemate\_foldinv -- fold inverters into Gatemate LUT trees} +\label{cmd:gatemate_foldinv} +\begin{lstlisting}[numbers=left,frame=single] + gatemate_foldinv [selection] + + +This pass searches for $__CC_NOT cells and folds them into CC_LUT2, CC_L2T4 +and CC_L2T5 cells as created by LUT tree mapping. +\end{lstlisting} + +\section{glift -- create GLIFT models and optimization problems} +\label{cmd:glift} +\begin{lstlisting}[numbers=left,frame=single] + glift <command> [options] [selection] + +Augments the current or specified module with gate-level information flow tracking +(GLIFT) logic using the "constructive mapping" approach. Also can set up QBF-SAT +optimization problems in order to optimize GLIFT models or trade off precision and +complexity. + + +Commands: + + -create-precise-model + Replaces the current or specified module with one that has corresponding "taint" + inputs, outputs, and internal nets along with precise taint tracking logic. + For example, precise taint tracking logic for an AND gate is: + + y_t = a & b_t | b & a_t | a_t & b_t + + + -create-imprecise-model + Replaces the current or specified module with one that has corresponding "taint" + inputs, outputs, and internal nets along with imprecise "All OR" taint tracking + logic: + + y_t = a_t | b_t + + + -create-instrumented-model + Replaces the current or specified module with one that has corresponding "taint" + inputs, outputs, and internal nets along with 4 varying-precision versions of taint + tracking logic. Which version of taint tracking logic is used for a given gate is + determined by a MUX selected by an $anyconst cell. By default, unless the + `-no-cost-model` option is provided, an additional wire named `__glift_weight` with + the `keep` and `minimize` attributes is added to the module along with pmuxes and + adders to calculate a rough estimate of the number of logic gates in the GLIFT model + given an assignment for the $anyconst cells. The four versions of taint tracking logic + for an AND gate are: + y_t = a & b_t | b & a_t | a_t & b_t (like `-create-precise-model`) + y_t = a_t | a & b_t + y_t = b_t | b & a_t + y_t = a_t | b_t (like `-create-imprecise-model`) + + +Options: + + -taint-constants + Constant values in the design are labeled as tainted. + (default: label constants as un-tainted) + + -keep-outputs + Do not remove module outputs. Taint tracking outputs will appear in the module ports + alongside the orignal outputs. + (default: original module outputs are removed) + + -simple-cost-model + Do not model logic area. Instead model the number of non-zero assignments to $anyconsts. + Taint tracking logic versions vary in their size, but all reduced-precision versions are + significantly smaller than the fully-precise version. A non-zero $anyconst assignment means + that reduced-precision taint tracking logic was chosen for some gate. + Only applicable in combination with `-create-instrumented-model`. + (default: use a complex model and give that wire the "keep" and "minimize" attributes) + + -no-cost-model + Do not model taint tracking logic area and do not create a `__glift_weight` wire. + Only applicable in combination with `-create-instrumented-model`. + (default: model area and give that wire the "keep" and "minimize" attributes) + + -instrument-more + Allow choice from more versions of (even simpler) taint tracking logic. A total + of 8 versions of taint tracking logic will be added per gate, including the 4 + versions from `-create-instrumented-model` and these additional versions: + + y_t = a_t + y_t = b_t + y_t = 1 + y_t = 0 + + Only applicable in combination with `-create-instrumented-model`. + (default: do not add more versions of taint tracking logic. +\end{lstlisting} + \section{greenpak4\_dffinv -- merge greenpak4 inverters and DFF/latches} \label{cmd:greenpak4_dffinv} \begin{lstlisting}[numbers=left,frame=single] @@ -2231,6 +2389,9 @@ resolves positional module parameters, unrolls array instances, and more. like -check, but also throw an error if blackbox modules are instantiated, and throw an error if the design has no top module. + -smtcheck + like -simcheck, but allow smtlib2_module modules. + -purge_lib by default the hierarchy command will not remove library (blackbox) modules. use this option to also remove unused blackbox modules. @@ -2402,26 +2563,28 @@ Map module inputs/outputs to PAD cells from a library. This pass can only map to very simple PAD cells. Use 'techmap' to further map the resulting cells to more sophisticated PAD cells. - -inpad <celltype> <portname>[:<portname>] + -inpad <celltype> <in_port>[:<ext_port>] Map module input ports to the given cell type with the given output port name. if a 2nd portname is given, the - signal is passed through the pad call, using the 2nd + signal is passed through the pad cell, using the 2nd portname as the port facing the module port. - -outpad <celltype> <portname>[:<portname>] - -inoutpad <celltype> <portname>[:<portname>] + -outpad <celltype> <out_port>[:<ext_port>] + -inoutpad <celltype> <io_port>[:<ext_port>] Similar to -inpad, but for output and inout ports. - -toutpad <celltype> <portname>:<portname>[:<portname>] + -toutpad <celltype> <oe_port>:<out_port>[:<ext_port>] Merges $_TBUF_ cells into the output pad cell. This takes precedence over the other -outpad cell. The first portname is the enable input - of the tristate driver. + of the tristate driver, which can be prefixed with `~` for negative + polarity enable. - -tinoutpad <celltype> <portname>:<portname>:<portname>[:<portname>] + -tinoutpad <celltype> <oe_port>:<in_port>:<out_port>[:<ext_port>] Merges $_TBUF_ cells into the inout pad cell. This takes precedence over the other -inoutpad cell. The first portname is the enable input of the tristate driver and the 2nd portname is the internal output - buffering the external signal. + buffering the external signal. Like with `-toutpad`, the enable can + be marked as negative polarity by prefixing the name with `~`. -ignore <celltype> <portname>[:<portname>]* Skips mapping inputs/outputs that are already connected to given @@ -2442,6 +2605,28 @@ the resulting cells to more sophisticated PAD cells. Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode. \end{lstlisting} +\section{jny -- write design and metadata} +\label{cmd:jny} +\begin{lstlisting}[numbers=left,frame=single] + jny [options] [selection] + +Write a JSON netlist metadata for the current design + + -o <filename> + write to the specified file. + + -no-connections + Don't include connection information in the netlist output. + + -no-attributes + Don't include attributed information in the netlist output. + + -no-properties + Don't include property information in the netlist output. + +See 'help write_jny' for a description of the JSON format used. +\end{lstlisting} + \section{json -- write design in JSON format} \label{cmd:json} \begin{lstlisting}[numbers=left,frame=single] @@ -2572,14 +2757,15 @@ is used then the $macc cell is mapped to $add, $sub, etc. cells instead. \section{memory -- translate memories to basic cells} \label{cmd:memory} \begin{lstlisting}[numbers=left,frame=single] - memory [-nomap] [-nordff] [-nowiden] [-nosat] [-memx] [-bram <bram_rules>] [selection] + memory [-norom] [-nomap] [-nordff] [-nowiden] [-nosat] [-memx] [-no-rw-check] [-bram <bram_rules>] [selection] This pass calls all the other memory_* passes in a useful order: opt_mem opt_mem_priority opt_mem_feedback - memory_dff (skipped if called with -nordff or -memx) + memory_bmux2rom (skipped if called with -norom) + memory_dff [-no-rw-check] (skipped if called with -nordff or -memx) opt_clean memory_share [-nowiden] [-nosat] opt_mem_widen @@ -2593,6 +2779,14 @@ This converts memories to word-wide DFFs and address decoders or multiport memory blocks if called with the -nomap option. \end{lstlisting} +\section{memory\_bmux2rom -- convert muxes to ROMs} +\label{cmd:memory_bmux2rom} +\begin{lstlisting}[numbers=left,frame=single] + memory_bmux2rom [options] [selection] + +This pass converts $bmux cells with constant A input to ROMs. +\end{lstlisting} + \section{memory\_bram -- map memories to block rams} \label{cmd:memory_bram} \begin{lstlisting}[numbers=left,frame=single] @@ -2706,11 +2900,45 @@ memory cells. \section{memory\_dff -- merge input/output DFFs into memory read ports} \label{cmd:memory_dff} \begin{lstlisting}[numbers=left,frame=single] - memory_dff [options] [selection] + memory_dff [-no-rw-check] [selection] This pass detects DFFs at memory read ports and merges them into the memory port. I.e. it consumes an asynchronous memory port and the flip-flops at its interface and yields a synchronous memory port. + + -no-rw-check + marks all recognized read ports as "return don't-care value on + read/write collision" (same result as setting the no_rw_check + attribute on all memories). +\end{lstlisting} + +\section{memory\_libmap -- map memories to cells} +\label{cmd:memory_libmap} +\begin{lstlisting}[numbers=left,frame=single] + memory_libmap -lib <library_file> [-D <condition>] [selection] + +This pass takes a description of available RAM cell types and maps +all selected memories to one of them, or leaves them to be mapped to FFs. + + -lib <library_file> + Selects a library file containing RAM cell definitions. This option + can be passed more than once to select multiple libraries. + See passes/memory/memlib.md for description of the library format. + + -D <condition> + Enables a condition that can be checked within the library file + to eg. select between slightly different hardware variants. + This option can be passed any number of times. + + -logic-cost-rom <num> + -logic-cost-ram <num> + Sets the cost of a single bit for memory lowered to soft logic. + + -no-auto-distributed + -no-auto-block + -no-auto-huge + Disables automatic mapping of given kind of RAMs. Manual mapping + (using ram_style or other attributes) is still supported. \end{lstlisting} \section{memory\_map -- translate multiport memories to basic cells} @@ -2732,6 +2960,12 @@ pass to word-wide DFFs and address decoders. -iattr for -attr, ignore case of <value>. + + -rom-only + only perform conversion for ROMs (memories with no write ports). + + -keepdc + when mapping ROMs, keep x-bits shared across read ports. \end{lstlisting} \section{memory\_memx -- emulate vlog sim behavior for mem ports} @@ -3098,6 +3332,15 @@ It also performs some simple expression rewriting. replaced by 'a'. the -keepdc option disables all such optimizations. \end{lstlisting} +\section{opt\_ffinv -- push inverters through FFs} +\label{cmd:opt_ffinv} +\begin{lstlisting}[numbers=left,frame=single] + opt_ffinv [selection] + +This pass pushes inverters to the other side of a FF when they can be merged +into LUTs on the other side. +\end{lstlisting} + \section{opt\_lut -- optimize LUT cells} \label{cmd:opt_lut} \begin{lstlisting}[numbers=left,frame=single] @@ -3184,6 +3427,9 @@ are then merged to one cell. -share_all Operate on all cell types, not just built-in types. + + -keepdc + Do not merge flipflops with don't-care bits in their initial value. \end{lstlisting} \section{opt\_muxtree -- eliminate dead trees in multiplexer trees} @@ -3420,6 +3666,7 @@ This pass calls all the other proc_* passes in the most common order. proc_prune proc_init proc_arst + proc_rom proc_mux proc_dlatch proc_dff @@ -3435,6 +3682,9 @@ The following options are supported: -nomux Will omit the proc_mux pass. + -norom + Will omit the proc_rom pass. + -global_arst [!]<netname> This option is passed through to proc_arst. @@ -3541,6 +3791,14 @@ a later assignment to the same signal and removes them. This pass identifies unreachable branches in decision trees and removes them. \end{lstlisting} +\section{proc\_rom -- convert switches to ROMs} +\label{cmd:proc_rom} +\begin{lstlisting}[numbers=left,frame=single] + proc_rom [selection] + +This pass converts switches into read-only memories when appropriate. +\end{lstlisting} + \section{qbfsat -- solve a 2QBF-SAT problem in the circuit} \label{cmd:qbfsat} \begin{lstlisting}[numbers=left,frame=single] @@ -3984,10 +4242,12 @@ Assign names auto-generated from the src attribute to all selected wires and cells with private names. - rename -wire [selection] + rename -wire [selection] [-suffix <suffix>] Assign auto-generated names based on the wires they drive to all selected cells with private names. Ignores cells driving privatly named wires. +By default, the cell is named after the wire with the cell type as suffix. +The -suffix option can be used to set the suffix to the given string instead. rename -enumerate [-pattern <pattern>] [selection] @@ -4323,15 +4583,16 @@ described here. -unset <name> do not modify the current selection. instead remove a previously saved selection under the given name (see @<name> below). + -assert-none do not modify the current selection. instead assert that the given - selection is empty. i.e. produce an error if any object matching the - selection is found. + selection is empty. i.e. produce an error if any object or module + matching the selection is found. -assert-any do not modify the current selection. instead assert that the given - selection is non-empty. i.e. produce an error if no object matching - the selection is found. + selection is non-empty. i.e. produce an error if no object or module + matching the selection is found. -assert-count N do not modify the current selection. instead assert that the given @@ -4705,7 +4966,7 @@ to a graphics file (usually SVG or PostScript). (including inout ports) are on the right side. -pause - wait for the use to press enter to before returning + wait for the user to press enter to before returning -enum enumerate objects with internal ($-prefixed) names @@ -4798,12 +5059,28 @@ This command simulates the circuit using the given top-level module. -vcd <filename> write the simulation results to the given VCD file + -fst <filename> + write the simulation results to the given FST file + + -aiw <filename> + write the simulation results to an AIGER witness file + (requires a *.aim file via -map) + + -x + ignore constant x outputs in simulation file. + + -date + include date and full version info in output. + -clock <portname> name of top-level clock input -clockn <portname> name of top-level clock input (inverse polarity) + -multiclock + mark that witness file is multiclock. + -reset <portname> name of top-level reset input (active high) @@ -4820,14 +5097,48 @@ This command simulates the circuit using the given top-level module. include the specified timescale declaration in the vcd -n <integer> - number of cycles to simulate (default: 20) + number of clock cycles to simulate (default: 20) -a - include all nets in VCD output, not just those with public names + use all nets in VCD/FST operations, not just those with public names -w writeback mode: use final simulation state as new init state + -r + read simulation results file (file formats supported: FST, VCD, AIW and WIT) + VCD support requires vcd2fst external tool to be present + + -map <filename> + read file with port and latch symbols, needed for AIGER witness input + + -scope <name> + scope of simulation top model + + -at <time> + sets start and stop time + + -start <time> + start co-simulation in arbitary time (default 0) + + -stop <time> + stop co-simulation in arbitary time (default END) + + -sim + simulation with stimulus from FST (default) + + -sim-cmp + co-simulation expect exact match + + -sim-gold + co-simulation, x in simulation can match any value in FST + + -sim-gate + co-simulation, x in FST can match any value in simulation + + -q + disable per-cycle/sample log message + -d enable debug output \end{lstlisting} @@ -4907,6 +5218,15 @@ This command splits multi-bit nets into single-bit nets. and split nets so that no driver drives only part of a net. \end{lstlisting} +\section{sta -- perform static timing analysis} +\label{cmd:sta} +\begin{lstlisting}[numbers=left,frame=single] + sta [options] [selection] + +This command performs static timing analysis on the design. (Only considers +paths within a single module, so the design must be flattened.) +\end{lstlisting} + \section{stat -- print some statistics} \label{cmd:stat} \begin{lstlisting}[numbers=left,frame=single] @@ -5023,6 +5343,11 @@ on partly selected designs. -flowmap use FlowMap LUT techmapping instead of ABC + -no-rw-check + marks all recognized read ports as "return don't-care value on + read/write collision" (same result as setting the no_rw_check + attribute on all memories). + The following commands are executed by this synthesis command: @@ -5171,6 +5496,9 @@ This command runs synthesis for Anlogic FPGAs. -nolutram do not use EG_LOGIC_DRAM16X4 cells in output netlist + -nobram + do not use EG_PHY_BRAM or EG_PHY_BRAM32K cells in output netlist + The following commands are executed by this synthesis command: @@ -5187,10 +5515,9 @@ The following commands are executed by this synthesis command: coarse: synth -run coarse - map_lutram: (skip if -nolutram) - memory_bram -rules +/anlogic/lutrams.txt - techmap -map +/anlogic/lutrams_map.v - setundef -zero -params t:EG_LOGIC_DRAM16X4 + map_ram: + memory_libmap -lib +/anlogic/lutrams.txt -lib +/anlogic/brams.txt [-no-auto-block] [-no-auto-distributed] (-no-auto-block if -nobram, -no-auto-distributed if -nolutram) + techmap -map +/anlogic/lutrams_map.v -map +/anlogic/brams_map.v map_ffram: opt -fast -mux_undef -undriven -fine @@ -5454,6 +5781,11 @@ This command runs synthesis for ECP5 FPGAs. -nodsp do not map multipliers to MULT18X18D + -no-rw-check + marks all recognized read ports as "return don't-care value on + read/write collision" (same result as setting the no_rw_check + attribute on all memories). + The following commands are executed by this synthesis command: @@ -5483,20 +5815,16 @@ The following commands are executed by this synthesis command: chtype -set $mul t:$__soft_mul (unless -nodsp) alumacc opt - memory -nomap + memory -nomap [-no-rw-check] opt_clean - map_bram: (skip if -nobram) - memory_bram -rules +/ecp5/brams.txt - techmap -map +/ecp5/brams_map.v - - map_lutram: (skip if -nolutram) - memory_bram -rules +/ecp5/lutrams.txt - techmap -map +/ecp5/lutrams_map.v + map_ram: + memory_libmap -lib +/ecp5/lutrams.txt -lib +/ecp5/brams.txt [-no-auto-block] [-no-auto-distributed] (-no-auto-block if -nobram, -no-auto-distributed if -nolutram) + techmap -map +/ecp5/lutrams_map.v -map +/ecp5/brams_map.v map_ffram: opt -fast -mux_undef -undriven -fine - memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block -attr syn_ramstyle=auto -attr syn_ramstyle=registers -attr syn_romstyle=auto -attr syn_romstyle=logic + memory_map opt -undriven -fine map_gates: @@ -5592,9 +5920,10 @@ The following commands are executed by this synthesis command: coarse: synth -run coarse - memory_bram -rules +/efinix/brams.txt + + map_ram: + memory_libmap -lib +/efinix/brams.txt techmap -map +/efinix/brams_map.v - setundef -zero -params t:EFX_RAM_5K map_ffram: opt -fast -mux_undef -undriven -fine @@ -5639,6 +5968,155 @@ The following commands are executed by this synthesis command: write_json <file-name> \end{lstlisting} +\section{synth\_gatemate -- synthesis for Cologne Chip GateMate FPGAs} +\label{cmd:synth_gatemate} +\begin{lstlisting}[numbers=left,frame=single] + synth_gatemate [options] + +This command runs synthesis for Cologne Chip AG GateMate FPGAs. + + -top <module> + use the specified module as top module. + + -vlog <file> + write the design to the specified verilog file. Writing of an output + file is omitted if this parameter is not specified. + + -json <file> + write the design to the specified JSON file. Writing of an output file + is omitted if this parameter is not specified. + + -run <from_label>:<to_label> + only run the commands between the labels (see below). An empty + from label is synonymous to 'begin', and empty to label is + synonymous to the end of the command list. + + -noflatten + do not flatten design before synthesis. + + -nobram + do not use CC_BRAM_20K or CC_BRAM_40K cells in output netlist. + + -noaddf + do not use CC_ADDF full adder cells in output netlist. + + -nomult + do not use CC_MULT multiplier cells in output netlist. + + -nomx8, -nomx4 + do not use CC_MX{8,4} multiplexer cells in output netlist. + + -luttree + use new LUT tree mapping approach (EXPERIMENTAL). + + -dff + run 'abc' with -dff option + + -retime + run 'abc' with '-dff -D 1' options + + -noiopad + disable I/O buffer insertion (useful for hierarchical or + out-of-context flows). + + -noclkbuf + disable automatic clock buffer insertion. + +The following commands are executed by this synthesis command: + + begin: + read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v + hierarchy -check -top <top> + + prepare: + proc + flatten + tribuf -logic + deminout + opt_expr + opt_clean + check + opt -nodffe -nosdff + fsm + opt + wreduce + peepopt + opt_clean + muxpack + share + techmap -map +/cmp2lut.v -D LUT_WIDTH=4 + opt_expr + opt_clean + + map_mult: (skip if '-nomult') + techmap -map +/gatemate/mul_map.v + + coarse: + alumacc + opt + memory -nomap + opt_clean + + map_bram: (skip if '-nobram') + memory_libmap -lib +/gatemate/brams.txt + techmap -map +/gatemate/brams_map.v + + map_ffram: + opt -fast -mux_undef -undriven -fine + memory_map + opt -undriven -fine + + map_gates: + techmap -map +/techmap.v -map +/gatemate/arith_map.v + opt -fast + + map_io: (skip if '-noiopad') + iopadmap -bits -inpad CC_IBUF Y:I -outpad CC_OBUF A:O -toutpad CC_TOBUF ~T:A:O -tinoutpad CC_IOBUF ~T:Y:A:IO + clean + + map_regs: + opt_clean + dfflegalize -cell $_DFFE_????_ x -cell $_DLATCH_???_ x + techmap -map +/gatemate/reg_map.v + opt_expr -mux_undef + simplemap + opt_clean + + map_muxs: + muxcover -mux4 -mux8 + opt -full + techmap -map +/gatemate/mux_map.v + + map_luts: + abc -genlib +/gatemate/lut_tree_cells.genlib (with -luttree) + techmap -map +/gatemate/lut_tree_map.v (with -luttree) + gatemate_foldinv (with -luttree) + techmap -map +/gatemate/inv_map.v (with -luttree) + abc -dress -lut 4 (without -luttree) + clean + + map_cells: + techmap -map +/gatemate/lut_map.v + clean + + map_bufg: (skip if '-noclkbuf') + clkbufmap -buf CC_BUFG O:I + clean + + check: + hierarchy -check + stat -width + check -noinit + blackbox =A:whitebox + + vlog: + opt_clean -purge + write_verilog -noattr <file-name> + + json: + write_json <file-name> +\end{lstlisting} + \section{synth\_gowin -- synthesis for Gowin FPGAs} \label{cmd:synth_gowin} \begin{lstlisting}[numbers=left,frame=single] @@ -5690,6 +6168,11 @@ This command runs synthesis for Gowin FPGAs. This work is experimental. -abc9 use new ABC9 flow (EXPERIMENTAL) + -no-rw-check + marks all recognized read ports as "return don't-care value on + read/write collision" (same result as setting the no_rw_check + attribute on all memories). + The following commands are executed by this synthesis command: @@ -5704,16 +6187,11 @@ The following commands are executed by this synthesis command: deminout coarse: - synth -run coarse + synth -run coarse [-no-rw-check] - map_bram: (skip if -nobram) - memory_bram -rules +/gowin/brams.txt - techmap -map +/gowin/brams_map.v - - map_lutram: (skip if -nolutram) - memory_bram -rules +/gowin/lutrams.txt - techmap -map +/gowin/lutrams_map.v - setundef -params -zero t:RAM16S4 + map_ram: + memory_libmap -lib +/gowin/lutrams.txt -lib +/gowin/brams.txt [-no-auto-block] [-no-auto-distributed] (-no-auto-block if -nobram, -no-auto-distributed if -nolutram) + techmap -map +/gowin/lutrams_map.v -map +/gowin/brams_map.v map_ffram: opt -fast -mux_undef -undriven -fine @@ -5724,8 +6202,7 @@ The following commands are executed by this synthesis command: techmap -map +/techmap.v -map +/gowin/arith_map.v opt -fast abc -dff -D 1 (only if -retime) - splitnets - iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O -toutpad $__GW_TBUF OE:I:O -tinoutpad $__GW_IOBUF OE:O:I:IO (unless -noiopads) + iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O -toutpad TBUF ~OEN:I:O -tinoutpad IOBUF ~OEN:O:I:IO (unless -noiopads) map_ffs: opt_clean @@ -5743,6 +6220,7 @@ The following commands are executed by this synthesis command: opt_lut_ins -tech gowin setundef -undriven -params -zero hilomap -singleton -hicell VCC V -locell GND G + splitnets -ports (only if -vout used) clean autoname @@ -5753,7 +6231,7 @@ The following commands are executed by this synthesis command: blackbox =A:whitebox vout: - write_verilog -decimal -attr2comment -defparam -renameprefix gen <file-name> + write_verilog -simple-lhs -decimal -attr2comment -defparam -renameprefix gen <file-name> write_json <file-name> \end{lstlisting} @@ -5897,6 +6375,9 @@ This command runs synthesis for iCE40 FPGAs. -nobram do not use SB_RAM40_4K* cells in output netlist + -spram + enable automatic inference of SB_SPRAM256KA + -dsp use iCE40 UltraPlus DSP cells for large arithmetic @@ -5916,6 +6397,11 @@ This command runs synthesis for iCE40 FPGAs. -flowmap use FlowMap LUT techmapping instead of abc (EXPERIMENTAL) + -no-rw-check + marks all recognized read ports as "return don't-care value on + read/write collision" (same result as setting the no_rw_check + attribute on all memories). + The following commands are executed by this synthesis command: @@ -5943,7 +6429,7 @@ The following commands are executed by this synthesis command: techmap -map +/cmp2lut.v -D LUT_WIDTH=4 opt_expr opt_clean - memory_dff + memory_dff [-no-rw-check] wreduce t:$mul techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16 (if -dsp) select a:mul2dsp (if -dsp) @@ -5955,17 +6441,17 @@ The following commands are executed by this synthesis command: chtype -set $mul t:$__soft_mul (if -dsp) alumacc opt - memory -nomap + memory -nomap [-no-rw-check] opt_clean - map_bram: (skip if -nobram) - memory_bram -rules +/ice40/brams.txt - techmap -map +/ice40/brams_map.v + map_ram: + memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt -no-auto-huge [-no-auto-huge] [-no-auto-block] (-no-auto-huge unless -spram, -no-auto-block if -nobram) + techmap -map +/ice40/brams_map.v -map +/ice40/spram_map.v ice40_braminit map_ffram: opt -fast -mux_undef -undriven -fine - memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block -attr syn_ramstyle=auto -attr syn_ramstyle=registers -attr syn_romstyle=auto -attr syn_romstyle=logic + memory_map opt -undriven -fine map_gates: @@ -6138,7 +6624,7 @@ This command runs synthesis for ALM-based Intel FPGAs. -family <family> target one of: "cyclonev" - Cyclone V (default) - "cyclone10gx" - Cyclone 10GX + "arriav" - Arria V (non-GZ) "cyclone10gx" - Cyclone 10GX -vqm <file> write the design to the specified Verilog Quartus Mapping File. Writing of an @@ -6283,6 +6769,12 @@ This command runs synthesis for MachXO2 FPGAs. from label is synonymous to 'begin', and empty to label is synonymous to the end of the command list. + -nobram + do not use block RAM cells in output netlist + + -nolutram + do not use LUT RAM cells in output netlist + -noflatten do not flatten design before synthesis @@ -6309,6 +6801,10 @@ The following commands are executed by this synthesis command: coarse: synth -run coarse + map_ram: + memory_libmap -lib +/machxo2/lutrams.txt -lib +/machxo2/brams.txt [-no-auto-block] [-no-auto-distributed] (-no-auto-block if -nobram, -no-auto-distributed if -nolutram) + techmap -map +/machxo2/lutrams_map.v -map +/machxo2/brams_map.v + fine: memory_map opt -full @@ -6316,7 +6812,7 @@ The following commands are executed by this synthesis command: opt -fast map_ios: (unless -noiopad) - iopadmap -bits -outpad $__FACADE_OUTPAD I:O -inpad $__FACADE_INPAD O:I -toutpad $__FACADE_TOUTPAD OE:I:O -tinoutpad $__FACADE_TINOUTPAD OE:O:I:B A:top + iopadmap -bits -outpad $__FACADE_OUTPAD I:O -inpad $__FACADE_INPAD O:I -toutpad $__FACADE_TOUTPAD ~T:I:O -tinoutpad $__FACADE_TINOUTPAD ~T:O:I:B A:top attrmvcp -attr src -attr LOC t:$__FACADE_OUTPAD %x:+[O] t:$__FACADE_TOUTPAD %x:+[O] t:$__FACADE_TINOUTPAD %x:+[B] attrmvcp -attr src -attr LOC -driven t:$__FACADE_INPAD %x:+[I] @@ -6444,29 +6940,18 @@ The following commands are executed by this synthesis command: memory -nomap opt_clean - map_lram: (skip if -nolram) - memory_bram -rules +/nexus/lrams.txt - setundef -zero -params t:$__NX_PDPSC512K - techmap -map +/nexus/lrams_map.v - - map_bram: (skip if -nobram) - memory_bram -rules +/nexus/brams.txt - setundef -zero -params t:$__NX_PDP16K - techmap -map +/nexus/brams_map.v - - map_lutram: (skip if -nolutram) - memory_bram -rules +/nexus/lutrams.txt - setundef -zero -params t:$__NEXUS_DPR16X4 - techmap -map +/nexus/lutrams_map.v + map_ram: + memory_libmap -lib +/nexus/lutrams.txt -lib +/nexus/brams.txt -lib +/nexus/lrams.txt -no-auto-huge [-no-auto-block] [-no-auto-distributed] (-no-auto-block if -nobram, -no-auto-distributed if -nolutram) + techmap -map +/nexus/lutrams_map.v -map +/nexus/brams_map.v -map +/nexus/lrams_map.v map_ffram: opt -fast -mux_undef -undriven -fine - memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block -attr syn_ramstyle=auto -attr syn_ramstyle=registers -attr syn_romstyle=auto -attr syn_romstyle=logic + memory_map opt -undriven -fine map_gates: techmap -map +/techmap.v -map +/nexus/arith_map.v - iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad $__NX_TOUTPAD OE:I:O -tinoutpad $__NX_TINOUTPAD OE:O:I:B A:top (skip if '-noiopad') + iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top (skip if '-noiopad') opt -fast abc -dff -D 1 (only if -retime) @@ -6612,6 +7097,7 @@ The following commands are executed by this synthesis command: write_blif -attr -param -auto-top verilog: + write_verilog -noattr -nohex <file-name> \end{lstlisting} \section{synth\_sf2 -- synthesis for SmartFusion2 and IGLOO2 FPGAs} @@ -6851,17 +7337,10 @@ The following commands are executed by this synthesis command: memory -nomap opt_clean - map_uram: (only if '-uram') - memory_bram -rules +/xilinx/{family}_urams.txt - techmap -map +/xilinx/{family}_urams_map.v - - map_bram: (skip if '-nobram') - memory_bram -rules +/xilinx/{family}_brams.txt - techmap -map +/xilinx/{family}_brams_map.v - - map_lutram: (skip if '-nolutram') - memory_bram -rules +/xilinx/lut[46]_lutrams.txt - techmap -map +/xilinx/lutrams_map.v + map_memory: + memory_libmap [...] + techmap -map +/xilinx/lutrams_<family>_map.v + techmap -map +/xilinx/brams_<family>_map.v map_ffram: opt -fast -full @@ -6876,7 +7355,7 @@ The following commands are executed by this synthesis command: opt -fast map_cells: - iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top (skip if '-noiopad') + iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad OBUFT ~T:I:O -tinoutpad IOBUF ~T:O:I:IO A:top (skip if '-noiopad') techmap -map +/techmap.v -map +/xilinx/cells_map.v clean @@ -6928,6 +7407,10 @@ in order to avoid a name collision with the built in commands. If any arguments are specified, these arguments are provided to the script via the standard $argc and $argv variables. + +Note, tcl will not recieve the output of any yosys command. If the output +of the tcl commands are needed, use the yosys command 'tee' to redirect yosys's +output to a temporary file. \end{lstlisting} \section{techmap -- generic technology mapper} @@ -7282,6 +7765,11 @@ This pass transforms $mux cells with 'z' inputs to tristate buffers. -logic convert tri-state buffers that do not drive output ports to non-tristate logic. this option implies -merge. + + -formal + convert all tri-state buffers to non-tristate logic and + add a formal assertion that no two buffers are driving the + same net simultaneously. this option implies -merge. \end{lstlisting} \section{uniquify -- create unique copies of modules} @@ -7313,7 +7801,7 @@ different compilation units. Additional -D<macro>[=<value>] options may be added after the option indicating the language version (and before file names) to set additional verilog defines. -The macros SYNTHESIS and VERIFIC are defined implicitly. +The macros YOSYS, SYNTHESIS, and VERIFIC are defined implicitly. verific -formal <verilog-file>.. @@ -7326,29 +7814,36 @@ Like -sv, but define FORMAL instead of SYNTHESIS. Load the specified VHDL files into Verific. - verific {-f|-F} <command-file> + verific {-f|-F} [-vlog95|-vlog2k|-sv2005|-sv2009| + -sv2012|-sv|-formal] <command-file> Load and execute the specified command file. - -Command file parser supports following commands: - +define - defines macro - -u - upper case all identifier (makes Verilog parser case insensitive) - -v - register library name (file) - -y - register library name (directory) - +incdir - specify include dir - +libext - specify library extension - +liborder - add library in ordered list - +librescan - unresolved modules will be always searched starting with the first - library specified by -y/-v options. - -f/-file - nested -f option - -F - nested -F option - - parse mode: +Override verilog parsing mode can be set. +The macros YOSYS, SYNTHESIS/FORMAL, and VERIFIC are defined implicitly. + +Command file parser supports following commands in file: + +define+<MACRO>=<VALUE> - defines macro + -u - upper case all identifier (makes Verilog parser + case insensitive) + -v <filepath> - register library name (file) + -y <filepath> - register library name (directory) + +incdir+<filepath> - specify include dir + +libext+<filepath> - specify library extension + +liborder+<id> - add library in ordered list + +librescan - unresolved modules will be always searched + starting with the first library specified + by -y/-v options. + -f/-file <filepath> - nested -f option + -F <filepath> - nested -F option (relative path) + parse files: + <filepath> + +systemverilogext+<filepath> + +verilog1995ext+<filepath> + +verilog2001ext+<filepath> + + analysis mode: -ams - +systemverilogext +v2k - +verilog1995ext - +verilog2001ext -sverilog @@ -7375,6 +7870,11 @@ Add Verilog library directories. Verific will search in this directories to find undefined modules. + verific -vlog-libext <extension>.. + +Add Verilog library extensions, used when searching in library directories. + + verific -vlog-define <macro>[=<value>].. Add Verilog defines. @@ -7430,6 +7930,9 @@ Import options: -v, -vv Verbose log messages. (-vv is even more verbose than -v.) + -pp <filename> + Pretty print design after elaboration to specified file. + The following additional import options are useful for debugging the Verific bindings (for Yosys and/or Verific developers): @@ -7470,50 +7973,6 @@ Pretty print options: Save output for VHDL design units. - verific -app <application>.. - -Execute YosysHQ formal application on loaded Verilog files. - -Application options: - - -module <module> - Run formal application only on specified module. - - -blacklist <filename[:lineno]> - Do not run application on modules from files that match the filename - or filename and line number if provided in such format. - Parameter can also contain comma separated list of file locations. - - -blfile <file> - Do not run application on locations specified in file, they can represent filename - or filename and location in file. - -Applications: - - WARNING: Applications only available in commercial build. - - - verific -template <name> <top_module>.. - -Generate template for specified top module of loaded design. - -Template options: - - -out - Specifies output file for generated template, by default output is stdout - - -chparam name value - Generate template using this parameter value. Otherwise default parameter - values will be used for templat generate functionality. This option - can be specified multiple times to override multiple parameters. - String values must be passed in double quotes ("). - -Templates: - - WARNING: Templates only available in commercial build. - - - verific -cfg [<name> [<value>]] Get/set Verific runtime flags. @@ -7594,6 +8053,9 @@ Options: Do not change the width of memory address ports. Use this options in flows that use the 'memory_memx' pass. + -mux_undef + remove 'undef' inputs from $mux, $pmux and $_MUX_ cells + -keepdc Do not optimize explicit don't-care values. \end{lstlisting} @@ -7629,6 +8091,9 @@ invariant constraints. -vmap <filename> like -map, but more verbose + -no-startoffset + make indexes zero based, enable using map files with smt solvers. + -I, -O, -B, -L If the design contains no input/output/assert/flip-flop then create one dummy input/output/bad_state-pin or latch to make the tools reading the @@ -8024,6 +8489,8 @@ Inside a script the input file can also can a here-document: Write a FIRRTL netlist of the current design. The following commands are executed by this command: pmuxtree + bmuxmap + demuxmap \end{lstlisting} \section{write\_ilang -- (deprecated) alias of write\_rtlil} @@ -8056,6 +8523,23 @@ a tool for Coarse-Grain Example-Driven Interconnect Synthesis. http://bygone.clairexen.net/intersynth/ \end{lstlisting} +\section{write\_jny -- generate design metadata} +\label{cmd:write_jny} +\begin{lstlisting}[numbers=left,frame=single] + jny [options] [selection] + + -no-connections + Don't include connection information in the netlist output. + + -no-attributes + Don't include attributed information in the netlist output. + + -no-properties + Don't include property information in the netlist output. + +Write a JSON metadata for the current design +\end{lstlisting} + \section{write\_json -- write design to a JSON file} \label{cmd:write_json} \begin{lstlisting}[numbers=left,frame=single] @@ -8115,6 +8599,7 @@ Where <port_details> is: "bits": <bit_vector> "offset": <the lowest bit index in use, if non-0> "upto": <1 if the port bit indexing is MSB-first> + "signed": <1 if the port is signed> } The "offset" and "upto" fields are skipped if their value would be 0.They don't affect connection semantics, and are only used to preserve originalHDL bit indexing.And <cell_details> is: @@ -8161,6 +8646,7 @@ And <net_details> is: "bits": <bit_vector> "offset": <the lowest bit index in use, if non-0> "upto": <1 if the port bit indexing is MSB-first> + "signed": <1 if the port is signed> } The "hide_name" fields are set to 1 when the name of this cell or net is |