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-rw-r--r--passes/cmds/rename.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 7d6d84d42..6326b4b15 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -104,7 +104,7 @@ static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell)
struct RenamePass : public Pass {
RenamePass() : Pass("rename", "rename object in the design") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -152,7 +152,7 @@ struct RenamePass : public Pass {
log("Rename top module.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string pattern_prefix = "_", pattern_suffix = "_";
bool flag_src = false;