diff options
Diffstat (limited to 'passes/cmds/rename.cc')
| -rw-r--r-- | passes/cmds/rename.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 7d6d84d42..f8fe715c8 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -104,7 +104,7 @@ static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell) struct RenamePass : public Pass { RenamePass() : Pass("rename", "rename object in the design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -152,7 +152,7 @@ struct RenamePass : public Pass { log("Rename top module.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { std::string pattern_prefix = "_", pattern_suffix = "_"; bool flag_src = false; @@ -290,11 +290,11 @@ struct RenamePass : public Pass { dict<RTLIL::Cell *, IdString> new_cell_names; for (auto wire : module->selected_wires()) - if (wire->name[0] == '\\' && wire->port_id == 0) + if (wire->name.isPublic() && wire->port_id == 0) new_wire_names[wire] = NEW_ID; for (auto cell : module->selected_cells()) - if (cell->name[0] == '\\') + if (cell->name.isPublic()) new_cell_names[cell] = NEW_ID; for (auto &it : new_wire_names) |