diff options
Diffstat (limited to 'passes/cmds/select.cc')
| -rw-r--r-- | passes/cmds/select.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 5d991d038..e0f1a6d69 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -380,7 +380,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0) selected_wires.insert(it.second); - for (auto &conn : mod->connections_) + for (auto &conn : mod->connections()) { std::vector<RTLIL::SigBit> conn_lhs = conn.first.to_sigbit_vector(); std::vector<RTLIL::SigBit> conn_rhs = conn.second.to_sigbit_vector(); @@ -396,7 +396,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v } for (auto &cell : mod->cells) - for (auto &conn : cell.second->connections_) + for (auto &conn : cell.second->connections()) { char last_mode = '-'; for (auto &rule : rules) { |