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-rw-r--r--passes/cmds/show.cc10
1 files changed, 5 insertions, 5 deletions
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 8ff068999..29b83a9aa 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -344,7 +344,7 @@ struct ShowWorker
std::vector<RTLIL::IdString> in_ports, out_ports;
- for (auto &conn : it.second->connections) {
+ for (auto &conn : it.second->connections_) {
if (!ct.cell_output(it.second->type, conn.first))
in_ports.push_back(conn.first);
else
@@ -368,7 +368,7 @@ struct ShowWorker
label_string += "}}";
std::string code;
- for (auto &conn : it.second->connections) {
+ for (auto &conn : it.second->connections_) {
code += gen_portbox(stringf("c%d:p%d", id2num(it.first), id2num(conn.first)),
conn.second, ct.cell_output(it.second->type, conn.first));
}
@@ -421,7 +421,7 @@ struct ShowWorker
fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name), proc_src.c_str());
}
- for (auto &conn : module->connections)
+ for (auto &conn : module->connections_)
{
bool found_lhs_wire = false;
for (auto &c : conn.first.chunks()) {
@@ -516,7 +516,7 @@ struct ShowWorker
log("Skipping blackbox module %s.\n", id2cstr(module->name));
continue;
} else
- if (module->cells.empty() && module->connections.empty() && module->processes.empty()) {
+ if (module->cells.empty() && module->connections_.empty() && module->processes.empty()) {
log("Skipping empty module %s.\n", id2cstr(module->name));
continue;
} else
@@ -695,7 +695,7 @@ struct ShowPass : public Pass {
for (auto &mod_it : design->modules) {
if (mod_it.second->get_bool_attribute("\\blackbox"))
continue;
- if (mod_it.second->cells.empty() && mod_it.second->connections.empty())
+ if (mod_it.second->cells.empty() && mod_it.second->connections_.empty())
continue;
if (design->selected_module(mod_it.first))
modcount++;